Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device

Abstract

A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film ( 10 ) constituting the channel forming region from an n type poly-crystalline silicon film ( 7 ) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film ( 10 ); and reducing an effective impurity concentration in the poly-crystalline silicon film ( 10 ).

1 . A vertical MISFET manufacturing method, comprising the steps of: 
 forming a lower semiconductor layer of a first conductivity type over a main surface of a semiconductor substrate;    forming a diffusion barrier layer over said lower semiconductor layer;    forming an intermediate semiconductor layer over said diffusion barrier layer;    performing, after said step of forming the intermediate semiconductor layer, a thermal treatment to said semiconductor substrate; and    patterning, after said step of performing the thermal treatment, at least said intermediate semiconductor layer and said lower semiconductor layer, thereby forming a columnar laminated structure,    wherein said lower semiconductor layer constitutes one of a source and drain of said vertical MISFET, a gate electrode of said vertical MISFET is formed on a sidewall of said intermediate semiconductor layer via a gate insulating film, and    an upper semiconductor layer constituting the other of the source and drain of said vertical MISFET is formed over said intermediate semiconductor layer.    
   
   
       2 . The vertical MISFET manufacturing method according to  claim 1 , 
 wherein a diffusion barrier layer is further formed between said upper semiconductor layer and said intermediate semiconductor layer.