Fabrication method of semiconductor integrated circuit device

Abstract

Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

1 . A fabrication method of semiconductor integrated circuit devices, comprising the steps of: 
 (a) preparing a semiconductor wafer which is partitioned into a plurality of chip areas, a semiconductor integrated circuit being formed in each of said plurality of chip areas, and over whose main face a plurality of first electrodes electrically connected to said semiconductor integrated circuits are formed;    (b) preparing a first card which holds a first sheet having a wiring electrically connected to a plurality of contact terminals for establishing contact with said plurality of first electrodes and said plurality of contact terminals so that tips of said plurality of contact terminals protrude toward the main face of said semiconductor wafer; and    (c) electrically inspecting said semiconductor integrated circuits by bringing said plurality of contact terminals into contact with said plurality of first electrodes,    wherein said tips of said plurality of contact terminals are arranged over a first face of said first sheet, and a plurality of second electrodes formed from part of said wiring are arranged over a second face of said first sheet, reverse to said first face,    wherein said first card has a first substrate electrically connected to said plurality of second electrodes and suppressing mechanisms for suppressing said plurality of contact terminals toward said plurality of first electrodes,    wherein said first substrate has a first circuit and over its main face a plurality of third electrodes electrically connected to said first circuit are formed,    wherein said plurality of third electrodes are electrically connected to the respectively matching ones of said plurality of second electrodes via first wires,    wherein said suppressing mechanisms are arranged above said plurality of contact terminals over said second face of said first sheet, and    wherein one of said suppressing mechanisms suppresses one or more of said contact terminals.    
   
   
       2 . The fabrication method of semiconductor integrated circuit devices according to  claim 1 , wherein said first wires electrically connected between said second electrodes and said third electrodes through which relatively large currents flow are relatively thicker than said first wires electrically connected between said second electrodes and said third electrodes through which relatively small currents flow.  
   
   
       3 . The fabrication method of semiconductor integrated circuit devices according to  claim 1 , wherein said wiring electrically connected to said contact terminals through which relatively large currents flow is relatively thicker than said wiring electrically connected to said contact terminals through which relatively small currents flow.  
   
   
       4 . The fabrication method of semiconductor integrated circuit devices according to  claim 1 , wherein an electronic element electrically connected to said first circuit is mounted over a surface of said first substrate.  
   
   
       5 . The fabrication method of semiconductor integrated circuit devices according to  claim 4 , wherein said electronic element constitutes a second circuit for performing said electrical inspection of said semiconductor integrated circuits.  
   
   
       6 . The fabrication method of semiconductor integrated circuit devices according to  claim 1 , wherein said main face of said semiconductor wafer is divided into a plurality of first areas, each of said plurality of chip areas is arranged in one or another of said plurality of first areas, and said step (c) is performed on each of said plurality of first areas.  
   
   
       7 . The fabrication method of semiconductor integrated circuit devices according to  claim 1 , 
 wherein said suppressing mechanisms are arranged above said plurality of contact terminals over said second face of said first sheet, and    wherein one of said suppressing mechanisms suppresses one of said contact terminals.