Semiconductor device incorporating fluorine into gate dielectric

Abstract

The invention provides, in one aspect, a method of fabricating a semiconductor device. This embodiment comprises depositing a gate layer over a gate dielectric layer located over a semiconductor substrate, and incorporating fluorine into the gate dielectric layer before doping the gate layer.

1 . A method of fabricating a semiconductor device, comprising: 
 forming a gate dielectric layer on a semiconductor substrate;    depositing a gate layer over the gate dielectric layer; and    incorporating fluorine into the gate dielectric layer;    doping the gate layer after incorporating fluorine into the gate dielectric layer.    
   
   
       2 . The method recited in  claim 1 , wherein incorporating comprises using a thermal anneal conducted at a temperature greater than about 850° C.  
   
   
       3 . The method recited in  claim 2 , wherein a processing temperature used to manufacture the semiconductor device does not exceed about 850° C. after the thermal anneal.  
   
   
       4 . The method recited in  claim 1 , further comprising patterning the gate layer after incorporating the fluorine.  
   
   
       5 . The method recited in  claim 1 , wherein doping comprises doping the gate layer with a dopant dose ranging from about 1e15 atoms/cm 2  to about 1e16 atoms/cm 2 .  
   
   
       6 . The method recited in  claim 1 , further comprising patterning the gate layer before incorporating the fluorine.  
   
   
       7 . The method recited in  claim 1 , wherein incorporating comprises implanting the fluorine at a dose ranging from about 1e14 atoms/cm 2  to about 5e15 atoms/cm 2 .  
   
   
       8 . The method recited in  claim 1 , wherein incorporating comprises using implanted fluorine or anneal in fluorine gas and diffusing the fluorine to an interface of the gate dielectric layer and the semiconductor substrate.  
   
   
       9 . A method of fabricating a semiconductor device, comprising: 
 forming gate electrodes over a semiconductor substrate, comprising:    depositing a gate layer over a gate dielectric layer; and    incorporating fluorine into the gate dielectric layer before doping the gate layer;    forming source/drains within the semiconductor substrate and adjacent the gate electrodes;    depositing dielectric layers over the gate electrodes; and    forming interconnects within and over the dielectric electrodes to interconnect the gate electrodes.    
   
   
       10 . The method recited in  claim 9 , wherein incorporating comprises using a thermal anneal conducted at a temperature greater than about 850° C.  
   
   
       11 . The method recited in  claim 10 , wherein a processing temperature used to manufacture the semiconductor device does not exceed about 850° C. after the thermal anneal.  
   
   
       12 . The method recited in  claim 9 , further comprising patterning the gate layer after incorporating the fluorine.  
   
   
       13 . The method recited in  claim 9 , further comprising doping the gate layer after incorporating.  
   
   
       14 . The method recited in  claim 13 , wherein doping comprises doping the gate layer with a dopant dose ranging from about 1e15 atoms/cm 2  to about 1e16 atoms/cm 2 .  
   
   
       15 . The method recited in  claim 9 , further comprising patterning the gate layer before incorporating the fluorine.  
   
   
       16 . The method recited in  claim 9 , wherein incorporating comprises implanting the fluorine at a dose ranging from about 1e14 atoms/cm 2  to about 5e15 atoms/cm 2 .  
   
   
       17 . The method recited in  claim 9 , wherein incorporating comprises using implanted fluorine or anneal in fluorine gas and diffusing the fluorine to an interface of the gate dielectric layer and the semiconductor substrate.  
   
   
       18 . A semiconductor device, comprising: 
 a gate dielectric layer on a substrate    a gate layer located over the gate dielectric layer, the gate layer being doped with a dopant;    and fluorine incorporated into the gate dielectric layer prior to the gate layer being doped with the dopant.