Dual depth shallow trench isolation and methods to form same

Abstract

Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth A between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench A depth by utilizing three dry etch steps.

1 . A fabrication process for forming dual depth trenches in a semiconductor memory device, the fabrication process comprising: 
 forming array trenches and periphery trenches into a semiconductor substrate by performing an etch process having a single dry etch step and which sets a side wall slope at the base of the array trenches to obtain a desired array trench depth and a desired the periphery trench depth so that the array trenches will close off at the base of the array trenches and the periphery trenches continue to be etched so that a trench Δ depth between the array trench depth and the periphery trench depth is obtained during the single dry etch step.    
   
   
       2 . The fabrication process as recited in  claim 1 , wherein the etch process comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow ratio of 12:2:(3-5).  
   
   
       3 . The fabrication process as recited in  claim 1 , wherein the etch process comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow ratio of approximately 12:2:(3-5), the flow ratio varying by 20%.  
   
   
       4 . The fabrication process as recited in  claim 1 , wherein the etch process comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow ratio of approximately 12:2:(3-5), the flow ratio varying by 50%.  
   
   
       5 . The fabrication process as recited in  claim 1 , wherein the etch process comprises utilizing an RF plasma etcher operated at 30 mTorr+/−10 mTorr, 800 W+/−200 W top RF power, 300 W+/−100 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow of HBr: 120 sccm+/−20 sccm, Cl 2 : 25 sccm+/−10 sccm, CH 2 F 2 : 30 sccm+/−10 sccm.  
   
   
       6 . A fabrication process for forming dual depth trench isolation in a semiconductor memory device, the fabrication process comprising: 
 forming array trenches and periphery trenches into a semiconductor substrate by performing an etch process comprising a single dry etch step which sets the side wall slope at the base of the array trenches to obtain a desired array trench depth and a desired the periphery trench depth so that the array trenches will close off at the base of the array trenches and the periphery trenches continue to be etched so that a trench Δ depth between the array trench depth and the periphery trench depth is obtained during the single dry etch step; and    filling the array trenches and the periphery trenches with an isolation material.    
   
   
       7 . The fabrication process as recited in  claim 6 , wherein the etch process comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow ratio of 12:2:(3-5).  
   
   
       8 . The fabrication process as recited in  claim 6 , wherein the etch process comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow ratio of approximately 12:2:(3-5), the flow ratio varying by 20%.  
   
   
       9 . The fabrication process as recited in  claim 6 , wherein the etch process comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow ratio of approximately 12:2:(3-5), the flow ratio varying by 50%.  
   
   
       10 . The fabrication process as recited in  claim 6 , wherein the etch process comprises utilizing an RF plasma etcher operated at 30 mTorr+/−10 mTorr, 800 W+/−200 W top RF power, 300 W+/−100 W bottom RF power, using an etch chemistry of HBr/CL 2 /CH 2 F 2  having a flow of HBr: 120 sccm+/−20 sccm, Cl 2 : 25 sccm+/−10 sccm, CH 2 F 2 : 30 sccm+/−10 sccm.  
   
   
       11 . A fabrication process for forming dual depth trenches in a semiconductor memory device, the fabrication process comprising: 
 performing a first dry etch step to form array trenches and periphery trenches into a semiconductor substrate having a pad oxide formed thereon, the pad oxide being thicker in a periphery section than in an array section, the first dry etch step stopping in the array section before clearing a silicon material at the base of the array trenches, and clearing a silicon material at the base of the periphery trench and stopping on the pad oxide in the periphery section;    performing a second dry etch to selectively etch the pad oxide at the bottom of periphery trench while in turn depositing a polymer on the sidewalls of silicon surfaces of the periphery trenches while depositing a polymer on the sidewalls and on the bottom of array trenches; and    performing a third dry etch to remove the polymer from the sidewalls of array trenches and periphery trenches while etching into the semiconductor substrate in the array section and the periphery section to achieve a desired trench depth in the array section and a desired trench depth the periphery section, thus creating a desired trench Δ depth between the array trench depth and the periphery trench depth.    
   
   
       12 . The fabrication process as recited in  claim 11 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of O 2 /He/CH 2 F 2  having a flow ratio of 3:7:60.  
   
   
       13 . The fabrication process as recited in  claim 11 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of O 2 /He/CH 2 F 2  having a flow ratio of approximately 3:7:60, the flow ratio varying by 20%.  
   
   
       14 . The fabrication process as recited in  claim 11 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of O 2 /He/CH 2 F 2  having a flow ratio of approximately 3:7:60, the flow ratio varying by 50%.  
   
   
       15 . The fabrication process as recited in  claim 11 , wherein the third dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/O 2 /He having a flow rate of approximately 20:(0-3):5.  
   
   
       16 . A fabrication process for forming dual depth trench isolation in a semiconductor memory device, the fabrication process comprising: 
 performing a first dry etch step to form array trenches and periphery trenches into a semiconductor substrate having a pad oxide formed thereon, the pad oxide being thicker in a periphery section than in an array section, the first dry etch step stopping in the array section before clearing a silicon material at the base of the array trenches, and clearing a silicon material at the base of the periphery trench and stopping on the pad oxide in the periphery section;    performing a second dry etch to selectively etch the pad oxide at the bottom of periphery trench while in turn depositing a polymer on the sidewalls of silicon surfaces of the periphery trenches while depositing a polymer on the sidewalls and on the bottom of array trenches;    performing a third dry etch to remove the polymer from the sidewalls of array trenches and periphery trenches while etching into semiconductor substrate in the array section and the periphery section to achieve a desired trench depth in the array section and a desired trench depth the periphery section, thus creating a desired trench Δ depth between the array trench depth and the periphery trench depth; and    filling the array trenches and the periphery trenches with an isolation material.    
   
   
       17 . The fabrication process as recited in  claim 16 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of O 2 /He/CH 2 F 2  having a flow ratio of 3:7:60.  
   
   
       18 . The fabrication process as recited in  claim 16 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of O 2 /He/CH 2 F 2  having a flow ratio of approximately 3:7:60, the flow ratio varying by 20%.  
   
   
       19 . The fabrication process as recited in  claim 16 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of O 2 /He/CH 2 F 2  having a flow ratio of approximately 3:7:60, the flow ratio varying by 50%.  
   
   
       20 . The fabrication process as recited in  claim 16 , wherein the third dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/O 2 /He having a flow rate of approximately 20:(0-3):5.  
   
   
       21 . A fabrication process for forming dual depth trenches in a semiconductor memory device, the fabrication process comprising the steps of: 
 performing a first dry etch step to etch array trenches and a periphery trench into a silicon substrate to a desired depth;    performing a second dry etch is performed to increase the depth of the array trenches and the periphery trench while depositing a polymer on the sidewalls of the array trenches and the sidewalls of the periphery trench and covering the bottom of the array trenches but not the bottom of periphery trench to create a desired trench Δ depth between the array trench depth and the periphery trench depth; and    performing a third etch step to remove any remaining polymer deposited in the bottom of the array trenches and to remove any induced kinks from the sidewall of the periphery trenches.    
   
   
       22 . The fabrication process as recited in  claim 21 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/CL 2 /CH 2 F 2  having a flow ratio of 12:2:(3-5).  
   
   
       23 . The fabrication process as recited in  claim 21 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/CL 2 /CH 2 F 2  having a flow ratio of approximately 12:2:(3-5), the flow ratio varying by 20%.  
   
   
       24 . The fabrication process as recited in  claim 21 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/CL 2 /CH 2 F 2  having a flow ratio of approximately 12:2:(3-5), the flow ratio varying by 50%.  
   
   
       25 . The fabrication process as recited in  claim 21 , wherein the third dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of CF 4 /He/NF 3  having a flow ratio of approximately 10:12:(1-2).  
   
   
       26 . The fabrication process as recited in  claim 21 , wherein the third dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of CF 4 /He/NF 3  having a flow ratio of 10:12:(1-2).  
   
   
       27 . The fabrication process as recited in  claim 21 , wherein the third dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of CF 4 /He/NF 3  having a flow ratio of 10:12:(1-2), the flow ratio varying by 20%.  
   
   
       28 . The fabrication process as recited in  claim 21 , wherein the third dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of CF 4 /He/NF 3  having a flow ratio of 10:12:(1-2), the flow ratio varying by 50%.  
   
   
       29 . A fabrication process for forming dual depth trenches in a semiconductor memory device, the fabrication process comprising the steps of: 
 performing a first dry etch step to etch array trenches and a periphery trench into a silicon substrate to a desired depth;    performing a second dry etch is performed to increase the depth of the array trenches and the periphery trench while depositing a polymer on the sidewalls of the array trenches and the sidewalls of the periphery trench and covering the bottom of the array trenches but not the bottom of the periphery trench to create a desired trench Δ depth between the array trench depth and the periphery trench depth;    performing a third etch step to remove any remaining polymer deposited in the bottom of the array trenches and to remove any induced kinks from the sidewall of the periphery trench; and    filling the array trenches and the periphery trenches with an isolation material.    
   
   
       30 . The fabrication process as recited in  claim 29 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow ratio of 12:2:(3-5).  
   
   
       31 . The fabrication process as recited in  claim 29 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow ratio of approximately 12:2:(3-5), the flow ratio varying by 20%.  
   
   
       32 . The fabrication process as recited in  claim 29 , wherein the second dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl 2 /CH 2 F 2  having a flow ratio of approximately 12:2:(3-5), the flow ratio varying by 50%.  
   
   
       33 . The fabrication process as recited in  claim 29 , wherein the third dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of CF 4 /He/NF 3  having a flow ratio of 10:12:(1-2).  
   
   
       34 . The fabrication process as recited in  claim 29 , wherein the third dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of CF 4 /He/NF 3  having a flow ratio of 10:12:(1-2), the flow ratio varying by 20%.  
   
   
       35 . The fabrication process as recited in  claim 29 , wherein the third dry etch step comprises utilizing an RF plasma etcher operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of CF 4 /He/NF 3  having a flow ratio of 10:12:(1-2), the flow ratio varying by 50%.  
   
   
       36 . Dual depth trenches in a semiconductor memory device comprising: 
 array trenches and periphery trenches in a semiconductor substrate, the array trenches having sloped sidewalls that terminate at a v-shaped vortex; and    the periphery trenches having a depth greater than the array trenches.    
   
   
       37 . Dual depth isolation structures in a semiconductor memory device comprising: 
 array isolation structures and periphery isolation structures in a semiconductor substrate, the array isolation structures having sloped sidewalls that terminate at a v-shaped vortex; and    the periphery isolation structures having a depth greater than the array isolation structures.