Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same

Abstract

An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening extending to the insulating layer. The semiconductor layer has a sidewall and a surface, the surface is spaced apart from the insulating layer, and the sidewall extends from the surface towards the insulating layer. The process can also include forming a sidewall spacer adjacent to the sidewall, wherein the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the sidewall spacer.

1 . A process of forming an electronic device comprising: 
 patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer, wherein after patterning a semiconductor layer: 
 the semiconductor layer has a sidewall and a surface;  
 the surface is spaced apart from the insulating layer; and  
 the sidewall extends from the surface towards the insulating layer; and  
   forming a sidewall spacer adjacent to the sidewall, wherein the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface.    
     
     
         2 . The process of  claim 1 , wherein forming the sidewall spacer comprises forming the sidewall spacer such that a first elevation, corresponding to a highest point of the sidewall spacer, lies closer to a primary surface of the substrate as compared to a second elevation, corresponding to the surface of the semiconductor layer.  
     
     
         3 . The process of  claim 1 , wherein forming the sidewall spacer comprises forming the sidewall spacer, wherein as seen from a cross-sectional view, the sidewall spacer has a triangular shape.  
     
     
         4 . The process of  claim 1 , wherein forming the sidewall spacer comprises forming the sidewall spacer, wherein as seen from a cross-sectional view, the sidewall spacer has a parabolic shape.  
     
     
         5 . The process of  claim 1 , wherein forming the sidewall spacer comprises forming the sidewall spacer, wherein as seen from a cross-sectional view, the sidewall spacer has a rectangular shape.  
     
     
         6 . The process of  claim 1 , further comprising oxidizing the semiconductor layer, wherein: 
 the semiconductor layer includes a first corner and a second corner;    the first corner is adjacent to the surface, and the second corner is adjacent to the insulating layer;    the first corner becomes rounded during oxidizing the semiconductor layer; and    the second corner substantially maintains its shape during oxidizing the semiconductor layer.    
     
     
         7 . The process of  claim 6 , further comprising: 
 depositing an oxide layer that substantially fills the opening; and    polishing the oxide layer to remove a portion of the oxide layer lying outside the opening.    
     
     
         8 . The process of  claim 7 , further comprising: 
 forming a patterned oxidation-resistant layer over the semiconductor layer before patterning the semiconductor layer; and    removing the patterned oxidation-resistant layer after removing the material.    
     
     
         9 . The process of  claim 1 , wherein forming the sidewall spacer comprises depositing a nitride layer.  
     
     
         10 . The process of  claim 9 , wherein forming the first layer is performed using an inductively coupled plasma.  
     
     
         11 . The process of  claim 1 , further comprising: 
 forming a gate dielectric layer adjacent to the semiconductor layer; and    forming a gate electrode, wherein the gate dielectric layer lies between the semiconductor layer and the gate electrode.    
     
     
         12 . A process of forming an electronic device comprising: 
 forming a patterned oxidation-resistant layer over a semiconductor layer, wherein an insulating layer lies between a substrate and the semiconductor layer;    patterning the semiconductor layer to define an opening extending to the insulating layer, wherein after patterning the semiconductor layer: 
 the semiconductor layer has a sidewall and a surface;  
 the surface is spaced apart from the insulating layer; and  
 the sidewall extends from the surface towards the insulating layer;  
   forming a sidewall spacer adjacent to the sidewall, wherein: 
 the sidewall spacer includes a nitride material;  
 the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface; and  
 a first elevation, corresponding to a highest point of the sidewall spacer, lies closer to a primary surface of the substrate as compared to a second elevation, corresponding to the surface of the semiconductor layer;  
   oxidizing the semiconductor layer after forming the sidewall spacer, wherein: 
 the semiconductor layer includes a first corner and a second corner;  
 the first corner is adjacent to the surface, and the second corner is adjacent to the insulating layer;  
 the first corner becomes rounded during oxidizing the semiconductor layer; and  
 the second corner substantially maintains its shape during oxidizing the semiconductor layer;  
   depositing an oxide layer that substantially fills the opening;    polishing the oxide layer to remove a portion of the oxide layer lying outside the opening;    removing the patterned oxidation-resistant layer after removing the material;    forming a gate dielectric layer adjacent to the semiconductor layer; and    forming a gate electrode, wherein: 
 the gate dielectric layer lies between the semiconductor layer and the gate electrode; and  
 the gate dielectric layer and the gate electrode are part of an n-channel transistor.  
   
     
     
         13 . An electronic device comprising: 
 a substrate;    an insulating layer;    a semiconductor layer, wherein: 
 the insulating layer lies between the substrate and the semiconductor layer;  
 the semiconductor layer has a sidewall and a surface;  
 the surface is spaced apart from the insulating layer; and  
 the sidewall extends between the insulating layer and the surface; and  
   a field isolation region overlying the insulating layer and lying adjacent to the sidewall of the semiconductor layer, wherein the field isolation region includes a sidewall spacer that lies adjacent to the sidewall and is spaced apart from the surface.    
     
     
         14 . The electronic device of  claim 13 , wherein a first elevation, corresponding to a highest point of the sidewall spacer, lies closer to a primary surface of the substrate as compared to a second elevation, corresponding to the surface of the semiconductor layer.  
     
     
         15 . The electronic device of  claim 13 , wherein as seen from a cross-sectional view, the sidewall spacer has a triangular shape.  
     
     
         16 . The electronic device of  claim 13 , wherein as seen from a cross-sectional view, the sidewall spacer has a parabolic shape.  
     
     
         17 . The electronic device of  claim 13 , wherein as seen from a cross-sectional view, the sidewall spacer has a rectangular shape.  
     
     
         18 . The electronic device of  claim 13 , wherein: 
 the semiconductor layer includes a first corner and a second corner;    the first corner is adjacent to the surface, and the second corner is adjacent to the insulating layer; and    the first corner is more rounded as compared to the second corner.    
     
     
         19 . The electronic device of  claim 18 , further comprising an oxide material, wherein: 
 a combination of the oxide material and the sidewall spacer substantially fills the opening; and    the sidewall spacer comprises a nitride material.    
     
     
         20 . The electronic device of  claim 18 , further comprising: 
 a gate dielectric layer adjacent to the semiconductor layer; and    a gate electrode, wherein the gate dielectric layer lies between the semiconductor layer and the gate electrode.