Modified via bottom structure for reliability enhancement

Abstract

The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

1 . A method of forming an interconnect structure having a modified via bottom structure comprising the steps of: 
 forming a second dielectric layer atop a first dielectric layer having a metallic interconnect embedded therein;    forming at least one aperture within said second dielectric layer that extends to the metallic interconnect in said first dielectric layer;    forming a liner material in said at least one aperture;    partially removing said liner material at a bottom surface of said at least one aperture to create a kinked interface, while simultaneously depositing a second liner; and    forming a conductive material in said at least one aperture including said kinked interface.    
   
   
       2 . The method of  claim 1  wherein said forming said at least one aperture comprises forming a via opening and a line opening, wherein said via opening is formed prior to said line opening.  
   
   
       3 . The method of  claim 1  wherein said forming said at least one aperture comprises forming a via opening and a line opening, wherein said line opening is formed prior to said via opening.  
   
   
       4 . The method of  claim 1  wherein a patterned cap layer is formed on a surface of said first dielectric layer prior to forming said second dielectric layer.  
   
   
       5 . The method of  claim 1  wherein said partially removing said liner material and simultaneous deposition includes ion bombardment and sputtering.  
   
   
       6 . The method of  claim 4  wherein said ion bombardment includes one of Ar, He, Ne, Xe, N 2 , H 2 , NH 3  or N 2 H 2 .  
   
   
       7 . The method of  claim 4  wherein said ion bombardment leaves a portion of said first liner on a bottom wall of said via so as to form said kinked interface.  
   
   
       8 . The method of  claim 1  wherein said step of partially removing said liner material and simultaneous deposition is repeated at least once.  
   
   
       9 . The method of  claim 1  further comprising a sputter process which is performed after said partially removing said liner material and simultaneous deposition step.  
   
   
       10 . The method of  claim 1  further comprising forming a patterned hard mask atop said second dielectric layer prior to said forming said at least one aperture.  
   
   
       11 . The method of  claim 1  wherein said metallic interconnect and said conductive material both comprise Cu.