Memory Device Having a Delay Locked Loop and Multiple Power Modes

Abstract

A single chip dynamic random access memory has a memory core, including dynamic random access memory cells, and a clock receiver circuit to receive an external clock signal. A delay locked loop circuit is coupled to the clock receiver circuit. In a first power mode, the delay locked loop circuit and the clock receiver circuit are turned on. Power consumption in the first power mode is less than that consumed while in an active mode. In a second power mode, the delay locked loop circuit is turned off. The memory is configured to receive a command that specifies a power down mode, to turn off the delay locked loop circuit in response to the command that specifies the power down mode, and to operate the memory device in a standby power mode. The delay locked loop circuit and the clock receiver circuit are turned on in a standby mode.

1 . A single chip dynamic random access memory device, comprising: 
 a core that includes dynamic random access memory cells;    a clock receiver circuit to receive an external clock signal;    a delay locked loop circuit coupled to the clock receiver circuit, wherein:    during a first power mode the delay locked loop circuit and the clock receiver circuit are turned on; wherein power consumption in the first power mode is less than that consumed while in an active mode; and    during a second power mode, the delay locked loop circuit is turned off.    
   
   
       2 . The memory device of  claim 1 , wherein the second power mode is a power down mode.  
   
   
       3 . The memory device of  claim 2 , wherein during the second power mode, the clock receiver circuit is turned off.  
   
   
       4 . The memory device of  claim 3 , further including a first control line, coupled to the clock receiver circuit and the delay locked loop circuit, wherein, during the second power mode, the delay locked loop circuit and the clock receiver circuit are turned off using the first control line.  
   
   
       5 . The memory device of  claim 1 , wherein during a third power mode, the delay locked loop circuit is in a low power configuration and the clock receiver circuit is turned on.  
   
   
       6 . The memory device of  claim 5 , wherein the third power mode is a nap mode.  
   
   
       7 . The memory device of  claim 5 , wherein a resynchronization time of the delay locked loop circuit in the low power configuration is less than a resynchronization time of the delay locked loop circuit in the second power mode.  
   
   
       8 . A method of operation of a single chip dynamic random access memory device having a core of dynamic random access memory cells, a delay locked loop circuit, and a clock receiver circuit coupled to the delay locked loop circuit, the method comprising: 
 receiving a command that specifies a power down mode;    turning off the delay locked loop circuit in response to the command that specifies the power down mode; and    operating the memory device in a standby power mode, wherein the delay locked loop circuit and the clock receiver circuit are turned on in the standby mode.    
   
   
       9 . The method of  claim 8 , wherein during the power down mode, the clock receiver circuit is turned off.  
   
   
       10 . The method of  claim 8 , further including operating the memory device in a nap mode, wherein during the nap mode, the delay locked loop circuit is in a low power configuration and the clock receiver circuit is on.  
   
   
       11 . The method of  claim 10 , wherein a resynchronization time of the delay locked loop circuit in the low power configuration is less than a resynchronization time of the delay locked loop circuit in the power down mode.