Device and method for etching flash memory gate stacks comprising high-k dielectric

Abstract

In one implementation, a method for etching a flash memory high-k gate stack on a workpiece is provided which includes etching a conductive material layer in a low temperature plasma chamber and etching a high-k dielectric layer in a high temperature plasma chamber. The workpiece is transferred between the low temperature plasma chamber and the high temperature plasma chamber through a vacuum transfer chamber connecting the low temperature plasma chamber and the high temperature plasma chamber. In one embodiment, an integrated etch station for etching a high-k flash memory structure is provided, which includes an etch chamber configured for plasma etch processing of a conductive material layer connected via a transfer chamber to an etch chamber configured for plasma etch processing of a high-k dielectric layer.

1 . A method for etching a flash memory high-k gate stack on a workpiece, the method comprising: 
 a) etching a conductive material layer in a low temperature plasma chamber;    b) etching a high-k dielectric layer in a high temperature plasma chamber; and    c) transferring the workpiece between the low temperature plasma chamber and the high temperature plasma chamber through a vacuum transfer chamber connecting the low temperature plasma chamber and the high temperature plasma chamber.    
   
   
       2 . The method of  claim 1 , wherein etching the high-k material layer comprises plasma etching with a cathode temperature in a range above about 150 degrees Celsius.  
   
   
       3 . The method of  claim 2 , wherein etching the high-k material layer comprises plasma etching with a cathode temperature in a range above about 250 degrees Celsius.  
   
   
       4 . The method of  claim 1 , wherein etching the conductive material layer comprises etching the lower polysilicon layer with a cathode temperature below about 100 degrees Celsius.  
   
   
       5 . The method of  claim 4 , wherein etching the conductive material layer comprises etching the lower polysilicon layer with a cathode temperature below about 80 degrees Celsius.  
   
   
       6 . The method of  claim 1 , wherein etching the conductive material layer comprises etching a silicon comprising layer in the low temperature plasma chamber.  
   
   
       7 . The method of  claim 6 , wherein etching the conductive material layer comprises etching a polysilicon layer in the low temperature plasma chamber.  
   
   
       8 . The method of  claim 7 , wherein etching the polysilicon layer comprises etching with a cathode temperature below about 100 degrees Celsius.  
   
   
       9 . The method of  claim 8 , wherein etching the polysilicon layer comprises etching with a cathode temperature below about 80 degrees Celsius.  
   
   
       10 . The method of  claim 1 , wherein etching the conductive material layer comprises etching a metal comprising layer in the low temperature plasma chamber.  
   
   
       11 . The method of  claim 10 , wherein etching the conductive material layer comprises etching at least one layer comprising: (a) tungsten; (b) tungsten nitride; or (c) tungsten silicide.  
   
   
       12 . A method for etching a wafer to form high-k dielectric flash memory devices, the method comprising: 
 a) etching with a plasma in a low temperature chamber to define a control gate;    b) etching with a plasma in the low temperature chamber to define a floating gate;    c) etching a high-k interdielectric layer with plasma in a low temperature chamber; and    d) transferring the wafer through a vacuum chamber between the high temperature chamber and the low temperature chamber between plasma etch processes.    
   
   
       13 . The method of  claim 12 , wherein etching in the low temperature chamber comprises etching with a cathode temperature less than about 100 degrees Celsius.  
   
   
       14 . The method of  claim 12 , wherein etching in the high temperature chamber comprises etching with a cathode temperature greater than about 100 degrees Celsius.  
   
   
       15 . An integrated etch station for etching a high-k flash memory structure comprising: 
 a) a conductive material etch chamber configured for plasma etch processing of a conductive material layer;    b) a high-k etch chamber configured for plasma etch processing of a high-k dielectric layer; and    c) a transfer chamber connecting the low temperature chamber and the high temperature chamber for transporting wafers between the low temperature chamber and the high temperature chamber.    
   
   
       16 . The integrated etch station of  claim 15 , wherein the high-k etch chamber is configured to etch in a temperature range greater than about 100 degrees Celsius, and wherein the conductive material etch chamber is configured to etch in a temperature range below about 100 degrees Celsius.  
   
   
       17 . The integrated etch station of  claim 15 , wherein the high-k etch chamber is configured to etch in a temperature range greater than about 250 degrees Celsius, and wherein the conductive material etch chamber is configured to etch in a temperature range below about 85 degrees Celsius.  
   
   
       18 . The integrated etch station of  claim 15 , wherein the high-k etch chamber is a reactive ion etch chamber.  
   
   
       19 . The integrated etch station of  claim 15 , wherein the transfer chamber is a vacuum chamber.  
   
   
       20 . The integrated etch station of  claim 15 , wherein the conductive material etch chamber is configured for etching at least one of: (a) polysilicon; (b) tungsten; (c) tungsten nitride; or (d) tungsten silicide.