US2008016284A1PendingUtilityA1

Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction

Assignee: GOODMAN BENJIMAN LPriority: May 31, 2005Filed: Sep 28, 2007Published: Jan 17, 2008
Est. expiryMay 31, 2025(expired)· nominal 20-yr term from priority
G06F 12/0833G06F 2212/507
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Claims

Abstract

According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.

Claims

exact text as granted — not AI-modified
1 . A method of data processing in a data processing system having a plurality of cache memories distributed in said data processing system and coupled for communication by an interconnect fabric, said method comprising: 
 maintaining a predictor indicating a historical scope of broadcast on said interconnect fabric for one or more previous operations transmitted on the interconnect fabric; and    predictively selecting a scope of broadcast of a subsequent operation by reference to said predictor.    
   
   
       2 . The method of  claim 1 , wherein: 
 said data processing system includes at least first and second coherency domains; and    said predictively selecting comprises selecting a first scope of broadcast including both said first and second coherency domains in response to a first setting of said predictor and selecting a second scope of broadcast including said first coherency domain and excluding said second coherency domain in response to a second setting of said predictor.    
   
   
       3 . The method of  claim 1 , wherein said maintaining comprises maintaining said predictor at a lower level cache in said data processing system.  
   
   
       4 . The method of  claim 1 , wherein said maintaining comprises maintaining a plurality of predictors, wherein each of said plurality of predictors indicates a historical scope of broadcast of operations in a respective one of a plurality of operation classes.  
   
   
       5 . The method of  claim 1 , wherein said maintaining comprises maintaining a saturating counter that saturates toward to prediction of a narrower broadcast scope.  
   
   
       6 . The method of  claim 5 , and further comprising reversing a prediction indicated by said saturating counter in response to a setting of a mode field.  
   
   
       7 . A data processing system having a plurality of cache memories distributed in said data processing system, said data processing system comprising: 
 at least first and second coherency domains each containing at least one processing unit having a cache memory;    an interconnect fabric coupling said first and second coherency domains; and    scope prediction logic within the first coherency domain, said scope prediction logic including a predictor that indicates a historical scope of broadcast on said interconnect fabric for one or more previous operations transmitted on the interconnect fabric, wherein said scope prediction logic predictively selects a scope of broadcast of a subsequent operation by reference to said predictor.    
   
   
       8 . The data processing system of  claim 7 , wherein said scope prediction logic predictively selects a first scope of broadcast including both said first and second coherency domains in response to a first setting of said predictor and selects a second scope of broadcast including said first coherency domain and excluding said second coherency domain in response to a second setting of said predictor.  
   
   
       9 . The data processing system of  claim 7 , wherein said cache memory of said first coherency domain includes said scope prediction logic.  
   
   
       10 . The data processing system of  claim 7 , wherein said scope prediction logic includes a plurality of predictors that each indicates a historical scope of broadcast of operations in a respective one of a plurality of operation classes.  
   
   
       11 . The data processing system of  claim 7 , wherein said predictor comprises a saturating counter that saturates toward to prediction of a narrower broadcast scope.  
   
   
       12 . The data processing system of  claim 11 , wherein said scope prediction logic includes a mode field, and wherein said scope prediction logic reverses a prediction indicated by said saturating counter in response to a setting of said mode field.  
   
   
       13 . A cache memory for a data processing system including an interconnect fabric and at least first and second coherency domains each containing at least one processing unit, said cache memory comprising: 
 a data array;    a cache directory of contents of said data array; and    a cache controller including scope prediction logic, wherein said scope prediction logic includes a predictor that indicates a historical scope of broadcast on the interconnect fabric for one or more previous operations transmitted by said cache memory on the interconnect fabric, wherein said scope prediction logic predictively selects a scope of broadcast of a subsequent operation by reference to said predictor.    
   
   
       14 . The cache memory of  claim 13 , wherein said scope prediction logic predictively selects a first scope of broadcast including both said first and second coherency domains in response to a first setting of said predictor and selects a second scope of broadcast including said first coherency domain and excluding said second coherency domain in response to a second setting of said predictor.  
   
   
       15 . The cache memory of  claim 13 , wherein said scope prediction logic includes a plurality of predictors that each indicates a historical scope of broadcast of operations in a respective one of a plurality of operation classes.  
   
   
       16 . The cache memory of  claim 13 , wherein said predictor comprises a saturating counter that saturates toward to prediction of a narrower broadcast scope.  
   
   
       17 . A processing unit, comprising: 
 a cache memory in accordance with  claim 13;  and    at least one processor core coupled to said cache memory.

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