US2008042265A1PendingUtilityA1

Chip scale module package in bga semiconductor package

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Assignee: MERILO LEO APriority: Aug 15, 2006Filed: Aug 15, 2006Published: Feb 21, 2008
Est. expiryAug 15, 2026(~0.1 yrs left)· nominal 20-yr term from priority
Inventors:Leo A. MeriloEmmanuel EspirituDario S. Filoteo, Jr.Rachel Layda Abinan
H10W 90/754H10W 90/734H10W 90/732H10W 90/724H10W 90/722H10W 74/117H10W 74/00H10W 72/9415H10W 72/942H10W 72/923H10W 72/884H10W 72/877H10W 72/90H10W 72/50H10W 70/682H10W 70/681H10W 90/00
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Claims

Abstract

A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array (BGA) substrate, and an application die attached to the integrated passive device (IPD). A method of manufacturing a semiconductor package includes providing a ball grid array (BGA) substrate having integrated metal layer circuitry, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array (BGA) substrate, and attaching an application die to the integrated passive device (IPD).

Claims

exact text as granted — not AI-modified
1 . A semiconductor package comprising:
 a ball grid array (BGA) substrate having integrated metal layer circuitry;   a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array (BGA) substrate; and   an application die attached to the integrated passive device (IPD).   
   
   
       2 . The semiconductor package of  claim 1 , wherein the flip chip CSMP is attached to the BGA substrate using an adhesive material. 
   
   
       3 . The semiconductor package of  claim 2 , wherein the adhesive material further includes a solder paste or flux material. 
   
   
       4 . The semiconductor package of  claim 1 , wherein the application die is wirebonded to the metal layer circuitry of the BGA substrate to provide electrical connectivity. 
   
   
       5 . The semiconductor package of  claim 1 , wherein the application die is wirebonded to the CSMP to provide electrical connectivity. 
   
   
       6 . The semiconductor package of  claim 1 , wherein the CSMP is wirebonded to the metal layer circuitry of the BGA substrate to provide electrical connectivity. 
   
   
       7 . The semiconductor package of  claim 1 , wherein the application die further comprises a second IPD or an integrated circuit (IC) device. 
   
   
       8 . The semiconductor package of  claim 1 , further including an encapsulant formed over the CSMP for providing structural support to the CSMP within the semiconductor package. 
   
   
       9 . The semiconductor package of  claim 1 , wherein the CSMP includes a grounded flip chip die for enhanced thermal performance. 
   
   
       10 . A method of manufacturing a semiconductor package, comprising:
 providing a ball grid array (BGA) substrate having integrated metal layer circuitry;   attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array (BGA) substrate; and   attaching an application die to the integrated passive device (IPD).   
   
   
       11 . The method of manufacturing a semiconductor package of  claim 10 , wherein the flip chip CSMP is attached to the BGA substrate using an adhesive material. 
   
   
       12 . The method of manufacturing a semiconductor package of  claim 11 , wherein the adhesive material further includes a solder paste or flux material. 
   
   
       13 . The method of manufacturing a semiconductor package of  claim 10 , further including wirebonding the application die to the metal layer circuitry of the BGA substrate to provide electrical connectivity. 
   
   
       14 . The method of manufacturing a semiconductor package of  claim 10 , further including wirebonding the application die to the CSMP to provide electrical connectivity. 
   
   
       15 . The method of manufacturing a semiconductor package of  claim 10 , further including wirebonding the CSMP to the metal layer circuitry of the BGA substrate to provide electrical connectivity. 
   
   
       16 . The method of manufacturing a semiconductor package of  claim 10 , wherein the application die further comprises a second IPD or an integrated circuit (IC) device. 
   
   
       17 . The method of manufacturing a semiconductor package of  claim 1 , further including forming an encapsulant over the CSMP for providing structural support to the CSMP within the semiconductor package. 
   
   
       18 . The method of manufacturing a semiconductor package of  claim 10 , wherein the CSMP includes a grounded flip chip die for enhanced thermal performance. 
   
   
       19 . A semiconductor package comprising:
 a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity;   a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the cavity of the thermally-enhanced substrate; and   an application die attached to the integrated passive device (IPD).   
   
   
       20 . The semiconductor package of  claim 19 , wherein the flip chip CSMP is attached to the thermally-enhanced substrate using an adhesive material. 
   
   
       21 . The semiconductor package of  claim 19 , wherein the application die is attached to the integrated passive device using an adhesive material. 
   
   
       22 . The semiconductor package of  claim 19 , wherein the application die is wirebonded to a bond finger of the thermally-enhanced substrate to provide electrical connectivity. 
   
   
       23 . The semiconductor package of  claim 19 , wherein the application die is bonded to the flip chip CSMP package to provide electrical connectivity. 
   
   
       24 . The semiconductor package of  claim 19 , wherein the flip chip CSMP package is wirebonded to a bond finger of the thermally-enhanced package to provide electrical connectivity. 
   
   
       25 . The semiconductor package of  claim 19 , wherein the application die further comprises a second IPD or an integrated circuit (IC) device. 
   
   
       26 . The semiconductor package of  claim 19 , wherein the CSMP includes a thermally-enhanced flip chip die. 
   
   
       27 . The semiconductor package of  claim 19 , further including an encapsulant formed over the CSMP for providing structural support to the CSMP within the semiconductor package. 
   
   
       28 . A method of manufacturing a semiconductor package comprising:
 providing a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity;   attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the cavity of the thermally-enhanced substrate; and   attaching an application die to the integrated passive device (IPD).   
   
   
       29 . The method of manufacturing a semiconductor package of  claim 28 , wherein the flip chip CSMP is attached to the cavity of the thermally-enhanced substrate using an adhesive material. 
   
   
       30 . The method of manufacturing a semiconductor package of  claim 28 , wherein the application die is attached to the integrated passive device using an adhesive material. 
   
   
       31 . The method of manufacturing a semiconductor package of  claim 28 , wherein the application die is wirebonded to a bond finger of the thermally-enhanced substrate to provide electrical connectivity. 
   
   
       32 . The method of manufacturing a semiconductor package of  claim 28 , wherein the application die is bonded to the flip chip CSMP package to provide electrical connectivity. 
   
   
       33 . The method of manufacturing a semiconductor package of  claim 28 , wherein the flip chip CSMP package is wirebonded to a bond finger of the thermally-enhanced package to provide electrical connectivity. 
   
   
       34 . The method of manufacturing a semiconductor package of  claim 28 , wherein the application die further comprises a second IPD or an integrated circuit (IC) device. 
   
   
       35 . The method of manufacturing a semiconductor package of  claim 28 , wherein the CSMP includes a thermally-enhanced flip chip die. 
   
   
       36 . The method of manufacturing a semiconductor package of  claim 28 , further including an encapsulant formed over the CSMP for providing structural support to the CSMP within the semiconductor package. 
   
   
       37 . A semiconductor package, comprising:
 a ball grid array (BGA) substrate having integrated metal circuitry;   a wafer level chip scale package (WLCSP) attached to the ball grid array substrate, the wafer level chip scale package having a first integrated passive device (IPD); and   an application die attached to the integrated passive device (IPD).   
   
   
       38 . The semiconductor package of  claim 37 , wherein the WLCSP is attached to the BGA substrate, or the application die is attached to the IPD using an adhesive material. 
   
   
       39 . The semiconductor package of  claim 38 , wherein the adhesive material further includes solder paste or flux-reflow material. 
   
   
       40 . The semiconductor package of  claim 37 , wherein the application die further includes a second IPD or an integrated circuit (IC) device. 
   
   
       41 . The semiconductor device of  claim 37 , wherein the WLCSP is wirebonded to the integrated metal circuitry of the BGA substrate to provide electrical connectivity. 
   
   
       42 . The semiconductor device of  claim 37 , wherein a solder ball of the WLCSP is bonded to a ball pad located on the BGA substrate to provide electrical connectivity. 
   
   
       43 . The semiconductor device of  claim 37 , further including an encapsulant formed over the WLCSP to provide structural support to the WLCSP within the semiconductor package.

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