Method for improving transistor performance through reducing the salicide interface resistance

Abstract

An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

1 . A method comprising: 
 forming an insulator region on a substrate having a first lattice constant;    etching a source region and a drain region in the substrate, thereby defining a channel region located between the source region and the drain region, and beneath the insulator region;    depositing a semiconductor material in the source region and in the drain region, the semiconductor material having a second lattice constant larger than the first lattice constant;    wherein the semiconductor material in the source region and in the drain region creates compression in the channel region; and    forming contacts on the top surface of the semiconductor material in the source region and in the drain region;    wherein the contacts comprise an alloy of nickel and the semiconductor material.    
   
   
       2 . The method of  claim 1  wherein the semiconductor material is a silicon germanium alloy.  
   
   
       3 . The method of  claim 2  wherein the contacts comprise nickel silicon germanium silicide.  
   
   
       4 . The method of  claim 2  wherein the silicon germanium alloy has a germanium composition between 5% and 50%.  
   
   
       5 . The method of  claim 4  wherein the silicon germanium alloy has a germanium composition between 10% and 40%.  
   
   
       6 . The method of  claim 5  wherein the silicon germanium alloy has a germanium composition between 15% and 30%.  
   
   
       7 . The method of  claim 2  further comprising doping the silicon germanium alloy with a boron concentration between 1*1018/cm3 and 3*1021/cm3.  
   
   
       8 . The method of  claim 2  wherein the silicon germanium alloy is doped in situ during the deposition of the silicon germanium alloy.  
   
   
       9 . The method of  claim 3  further comprising etching the source region and the drain region laterally beneath the insulator region.  
   
   
       10 . A method comprising: 
 providing a substrate;    forming an insulator on the substrate;    forming and patterning a gate region atop the insulator;    etching a source region and a drain region in the substrate;    depositing a silicon germanium alloy in the source region and in the drain region;    wherein the silicon germanium alloy in the source region and in the drain region further creates compression in a substrate region located between the source region and drain region, and beneath the insulator; and    forming a nickel silicon germanium silicide layer on the top surface of the silicon germanium alloy in the source region and in the drain region.    
   
   
       11 . The method of  claim 10  further comprising depositing nickel on the surface of silicon germanium alloy in the source region and in the drain region prior to forming the nickel silicon germanium silicide layer.  
   
   
       12 . The method of  claim 11  wherein the nickel has a thickness between 50 and 200 angstroms.  
   
   
       13 . The method of  claim 10  wherein forming the nickel silicon germanium silicide layer further comprises: 
 depositing nickel on the surface of the silicon germanium alloy in the source region and in the drain region;    annealing the substrate at a temperature between 325° C. and 450° C. for less than or equal to 60 seconds;    removing excess nickel with a wet etch chemistry of hot H2O2 and H2SO4; and    annealing the substrate at a temperature between 400° C. and 550° C.    
   
   
       14 . The method of  claim 10  wherein forming the nickel silicon germanium silicide layer is a self aligned process.  
   
   
       15 . The method of  claim 10  further comprising etching the source region and the drain region laterally beneath the insulator.  
   
   
       16 . The  claim 15  further comprising etching the source region and the drain region laterally beneath the gate region.  
   
   
       17 . The method of  claim 16  further comprising etching the source region and the drain region between 25 angstroms and 200 angstroms laterally beneath the gate region.  
   
   
       18 . The method of  claim 10  further comprising etching the source region and the drain region a vertical depth between 100 angstroms and 1500 angstroms beneath the surface of the silicon substrate.  
   
   
       19 . The method of  claim 10  further comprising doping the silicon germanium alloy.  
   
   
       20 . The method of  claim 19  wherein the silicon germanium alloy is doped in situ during the deposition of the silicon germanium alloy.  
   
   
       21 . A transistor comprising: 
 an insulator region on a substrate having a first lattice constant;    a source region and a drain region in the substrate, thereby defining a channel region located between the source region and the drain region and beneath the insulator region, the source region and the drain region comprising a semiconductor material having a second lattice constant larger than the first lattice constant, wherein the semiconductor material creates compression in the channel region; and    contacts on the top surface of the semiconductor material in the source region and in the drain region, wherein the contacts comprise an alloy of nickel and the semiconductor material.    
   
   
       22 . The transistor of  claim 21 , wherein the semiconductor material is a silicon germanium alloy.  
   
   
       23 . The transistor of  claim 22 , wherein the contacts comprise nickel, silicon, germanium silicide.  
   
   
       24 . The transistor of  claim 22 , wherein the silicon germanium alloy has a germanium composition of between 5% and 50%.  
   
   
       25 . The transistor of  claim 24 , wherein the silicon germanium alloy has a germanium composition between 10% and 40%.  
   
   
       26 . The transistor of  claim 25 , wherein the silicon germanium alloy has a germanium composition between 15% and 30%.  
   
   
       27 . The transistor of  claim 22 , wherein the silicon germanium alloy is doped with boron to a concentration between 1×10 18 /cm 3  and 3×10 21 /cm 3 .  
   
   
       28 . The transistor of  claim 23 , wherein the semiconductor material in a source region and in the drain region extend laterally beneath the insulator region.