Non-volatile memory cell and non-volatile memory device using said cell

Abstract

A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer.

1 . A non-volatile memory cell comprising: 
 a dielectric charge trapping layer located substantially above a channel junction of the cell, said charge trapping layer being adapted to be charged and discharged more than 100 cycles before degrading beyond an operable state.    
   
   
       2 . The method according to  claim 1 , wherein said charge trapping layer is adapted to be charged and discharged more than 500 cycles before degrading beyond an operable state.  
   
   
       3 . The method according to  claim 1 , wherein said charge trapping layer is adapted to be charged and discharged more than 1500 cycles before degrading beyond an operable state.  
   
   
       4 . The method according to  claim 1 , wherein said charge trapping layer is adapted to be charged and discharged more than 2000 cycles before degrading beyond an operable state.  
   
   
       5 . The method according to  claim 1 , wherein said charge trapping layer is adapted to be charged and discharged more than 10,000 cycles before degrading beyond an operable state.  
   
   
       6 . A method of fabricating a non-volatile memory cell comprising: 
 depositing a dielectric charge trapping layer substantially above a channel junction of the cell, said charge trapping layer being adapted to be charged and discharged more than 100 cycles before degrading beyond an operable state.    
   
   
       7 . The method according to  claim 6 , wherein dielectric charge trapping is adapted to be charged and discharged more than 500 cycles before degrading beyond an operable state.  
   
   
       8 . The method according to  claim 6 , wherein dielectric charge trapping is adapted to be charged and discharged more than 1500 cycles before degrading beyond an operable state.  
   
   
       9 . The method according to  claim 6 , wherein dielectric charge trapping is adapted to be charged and discharged more than 2000 cycles before degrading beyond an operable state.  
   
   
       10 . The method according to  claim 6 , wherein dielectric charge trapping is Adapted to be charged and discharged more than 10,000 cycles before degrading beyond an operable state.  
   
   
       11 . A non volatile memory cell comprising: 
 A charge trapping layer comprised of an impure silicon based dielectric located substantially above a channel of the cell,    wherein said silicon based dielectric contains an impurity selected from the group consisting of oxygen, boron, carbon and polycrystalline silicon,    wherein said silicon based dielectric is selected from the group consisting of silicon dioxide and silicon nitride.    
   
   
       12 . The cell according to  claim 11 , wherein oxygen is introduced into said dielectric.  
   
   
       13 . A non-volatile memory cell comprising: 
 a charge trapping layer at least partially including silicon nitride, wherein    said silicon nitride includes an annealed nitride portion and at least a portion of which is located substantially above a channel of the cell.    
   
   
       14 . A non-volatile memory cell comprising: 
 a charge trapping layer and at least partially including silicon nitride, wherein said silicon nitride includes an annealed nitride portion and is located substantially below a gate of the cell.    
   
   
       15 . A non-volatile memory cell comprising: 
 two charge trapping regions, wherein each charge trapping region is located in proximity to and above a channel junction of said cell;    wherein a thickness of said two charge trapping regions is approximately 100 angstroms or less.    
   
   
       16 . The cell according to  claim 12  further comprising an oxide layer between said charge trapping regions and a channel of said cell.  
   
   
       17 . The cell according to  claim 12 , wherein a thickness of said oxide layer is 50 angstroms or greater.  
   
   
       18 . The cell according to  claim 12 , wherein a ratio of oxide thickness to trapping region thickness is 0.6 and 5.  
   
   
       19 . A non-volatile memory cell comprising: 
 two charge trapping regions, wherein each charge trapping region is located below a gate of said cell;    wherein a thickness of said two charge trapping regions is approximately 100 angstroms or less.    
   
   
       20 . The cell according to  claim 16 , further comprising an oxide layer between said charge trapping region and said channel.  
   
   
       21 . The cell according to  claim 16 , wherein a thickness of said oxide layer is 50 angstroms or greater.  
   
   
       22 . The cell according to  claim 16 , wherein a ratio of oxide thickness to trapping layer thickness is between 0.6 and 5.