Vents with signal image for signal return path

Abstract

A method for forming an electrical structure. A dielectric substrate having a metal signal line therein is provided. A first metal voltage plane is laminated to a first surface of the dielectric substrate. An opening in the first metal voltage plane is formed such that a first electrically conductive strip across the opening includes an image of a first portion of the metal signal line, wherein the image of the first portion of the metal signal line projects across the opening in the first metal voltage plane. A signal current is flowed through the metal signal line, wherein the signal current is an alternating current. A return current is flowed through the first electrically conductive strip, wherein the return current includes a portion of the signal current.

1 . A method for forming an electrical structure, comprising:
 providing a dielectric substrate having a metal signal line therein;   laminating a first metal voltage plane to a first surface of the dielectric substrate;   forming an opening in the first metal voltage plane such that a first electrically conductive strip across the opening includes an image of a first portion of the metal signal line, wherein the image of the first portion of the metal signal line projects across the opening in the first metal voltage plane;   flowing a signal current through the metal signal line, wherein the signal current is an alternating current; and   flowing a return current through the first electrically conductive strip, wherein the return current includes a portion of the signal current.   
   
   
       2 . The method of  claim 1 , further comprising:
 laminating a second metal voltage plane to a second surface of the dielectric substrate; and   forming an opening in the second metal voltage plane such that a second electrically conductive strip across the opening includes an image of a second portion of the metal signal line, wherein the image of the second portion of the metal signal line projects across the opening in the second metal voltage plane.   
   
   
       3 . The method of  claim 2 , further comprising:
 flowing a signal current through the metal signal line, wherein the signal current is an alternating current;   flowing a first return current through the first electrically conductive strip, wherein the first return current includes a first portion of the signal current; and   flowing a second return current through the second electrically conductive strip, wherein the second return current includes a second portion of the signal current.   
   
   
       4 . The method of  claim 2 , wherein the opening in the second metal voltage plane is not congruent to the opening in the first metal voltage plane. 
   
   
       5 . The method of  claim 2 , wherein the image of the second portion of the metal signal line is not congruent to the image of the first portion of the metal signal line. 
   
   
       6 . The method of  claim 2 , wherein the second electrically conductive strip is not congruent to the first electrically conductive strip. 
   
   
       7 . The method of  claim 2 , wherein the second electrically conductive strip is about congruent to the first electrically conductive strip 
   
   
       8 . The method of  claim 1 , wherein an electrical performance of the signal current and the return current is not degraded relative to a case in which the opening is not present. 
   
   
       9 . The method of  claim 1 , wherein said laminating the first metal voltage plane to the first surface of the dielectric substrate is performed before said forming the opening in the first metal voltage plane. 
   
   
       10 . The method of  claim 1 , wherein the opening in the first metal voltage plane has an outer boundary whose shape is elliptical. 
   
   
       11 . A method for forming an electrical structure, comprising:
 providing a dielectric substrate having a metal signal line therein;   laminating a first metal voltage plane to a first surface of the dielectric substrate, wherein the first metal voltage plane includes an opening, wherein an image of a first portion of the metal signal line projects across the opening in the first metal voltage plane, and wherein a first electrically conductive strip across the opening in the first metal voltage plane includes the image of the first portion; and   laminating a second metal voltage plane laminated to a second surface of the dielectric substrate, wherein the second metal voltage plane includes an opening, wherein an image of a second portion of the metal signal line projects across the opening in the second metal voltage plane, and wherein a second electrically conductive strip across the opening in the second metal voltage plane includes the image of the second portion;   flowing a signal current through the metal signal line, wherein the signal current is an alternating current;   flowing a first return current through the first electrically conductive strip, wherein the first return current includes a first portion of the signal current; and   flowing a second return current through the second electrically conductive strip, wherein the second return current includes a second portion of the signal current.   
   
   
       12 . The method of  claim 11 , wherein the opening in the first metal voltage plane has an outer boundary whose shape is circular or elliptical. 
   
   
       13 . The method of  claim 11 , wherein the opening in the second metal voltage plane is not congruent to the opening in the first metal voltage plane. 
   
   
       14 . The method of  claim 11 , wherein the image of the second portion of the metal signal line is not congruent to the image of the first portion of the metal signal line. 
   
   
       15 . The method of  claim 11 , wherein the second electrically conductive strip is not congruent to the first electrically conductive strip. 
   
   
       16 . The method of  claim 11 , wherein the second electrically conductive strip is congruent to the first electrically conductive strip. 
   
   
       17 . The method of  claim 11 , wherein the electrical structure comprises an electrical apparatus is a chip carrier, and wherein the electrical apparatus includes the dielectric substrate and the metal voltage plane. 
   
   
       18 . The method of  claim 11 , wherein the first electrically conductive strip is integral with the first metal voltage plane. 
   
   
       19 . The method of  claim 11 , wherein the first electrically conductive strip is linear across the opening in the first metal voltage plane.