MOSFET Device With Localized Stressor

Abstract

A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.

1 . A transistor formed on a substrate, the transistor comprising:
 a gate electrode formed on a gate dielectric layer, wherein the gate dielectric layer is located on the substrate;   spacers on the substrate alongside the gate electrode;   a source region in the substrate on a first side of the gate electrode;   a drain region in the substrate on a second side of the gate electrode; and   a film over the source and drain regions, the film not extending over the gate electrode and leaving at least a portion of the spacers exposed, the film imparting stress along a source-to-drain direction comprising a plurality of layers.   
   
   
       2 . The transistor of  claim 1 , wherein the transistor comprises an n-channel transistor and the film comprises a tensile-stress film. 
   
   
       3 . The transistor of  claim 2 , wherein the tensile-stress film comprises SiN, oxynitride, oxide, SiC, SiCN, Co silicide, Ni silicide, or combinations thereof. 
   
   
       4 . The transistor of  claim 1 , wherein the transistor comprises a p-channel transistor and the film comprises a compressive-stress film. 
   
   
       5 . The transistor of  claim 3 , wherein the compressive-stress film comprises SiN, oxynitride, oxide, SiGe, or combinations thereof. 
   
   
       6 . The transistor of  claim 1 , further comprising a contact etch-stop layer over the transistor and the film. 
   
   
       7 . The transistor of  claim 1 , wherein the film has a thickness between about 5 nm and about 500 nm. 
   
   
       8 . A transistor formed on a substrate, the transistor comprising:
 a gate electrode formed on a gate dielectric layer, wherein the gate dielectric layer is located on the substrate;   spacers on the substrate alongside the gate electrode;   source/drain regions formed in the substrate on either side of the gate electrode;   a high-stress film formed over the source/drain regions, the high-stress film not extending on top of the gate electrode; and   a contact etch-stop layer formed over the transistor and the high-stress film, the contact etch-stop layer contacting the spacers.   
   
   
       9 . The transistor of  claim 8 , wherein the transistor comprises an n-channel transistor and the high-stress film comprises a tensile-stress film. 
   
   
       10 . The transistor of  claim 9 , wherein the tensile-stress film comprises SiN, oxynitride, oxide, SiC, SiCN, Co silicide, Ni silicide, or combinations thereof. 
   
   
       11 . The transistor of  claim 8 , wherein the transistor comprises a p-channel transistor and the high-stress film comprises a compressive-stress film. 
   
   
       12 . The transistor of  claim 11 , wherein the compressive-stress film comprises SiN, oxynitride, oxide, SiGe, or combinations thereof. 
   
   
       13 . The transistor of  claim 8 , wherein the high-stress film comprises a plurality of films. 
   
   
       14 . The transistor of  claim 8 , wherein the high-stress film has a thickness between about 5 nm and about 500 nm. 
   
   
       15 . A transistor formed on a substrate, the transistor comprising:
 a gate electrode formed on a gate dielectric layer, wherein the gate dielectric layer is located on the substrate;   spacers on the substrate alongside the gate electrode;   a source region in the substrate on a first side of the gate electrode;   a drain region in the substrate on a second side of the gate electrode;   a multi-layer film over the source and drain regions, wherein the multi-layer film does not extend over the gate electrode and imparts stress along a source-to-drain direction; and   a contact etch-stop layer over the transistor, the film, and the spacers.   
   
   
       16 . The transistor of  claim 15 , wherein the transistor comprises an n-channel transistor and the film comprises a tensile-stress film. 
   
   
       17 . The transistor of  claim 16 , wherein the tensile-stress film comprises SiN, oxynitride, oxide, SiC, SiCN, Co silicide, Ni silicide, or combinations thereof. 
   
   
       18 . The transistor of  claim 15 , wherein the transistor comprises a p-channel transistor and the film comprises a compressive-stress film. 
   
   
       19 . The transistor of  claim 18 , wherein the compressive-stress film comprises SiN, oxynitride, oxide, SiGe, or combinations thereof. 
   
   
       20 . The transistor of  claim 15 , wherein the film has a thickness between about 5 nm and about 500 nm.