Semiconductor structures with structural homogeneity

Abstract

Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.

1 - 52 . (canceled) 
     
     
         53 . A semiconductor structure comprising:
 a substrate; and   a semiconductor layer disposed over the substrate, the semiconductor layer including at least two elements and having a top surface,   wherein the semiconductor layer top surface is substantially haze-free.   
     
     
         54 . The structure of  claim 53  wherein a portion of the semiconductor layer disposed below the top surface comprises a superlattice. 
     
     
         55 . The structure of  claim 53 , further comprising:
 a relaxed graded layer disposed between the substrate and the semiconductor layer.   
     
     
         56 . The structure of  claim 53  wherein the semiconductor layer top surface has a roughness root-mean-square of less than 5 angstroms in a scan area of 40 μm×40 μm, and a contamination level of less than 0.29 particles/cm 2 , the particles having a diameter greater than 0.12 micrometers. 
     
     
         57 . The structure of  claim 56  wherein the roughness is less than 1 angstrom root-mean-square in a scan area of 1 μm×1 μm. 
     
     
         58 . The structure of  claim 53  wherein the semiconductor layer top surface has a roughness of less than 5 angstroms root-mean-square in a scan area of 40 μm×40 μm and a contamination level of less than 0.16 particles/cm 2 , the particles having a diameter greater than 0.16 micrometers. 
     
     
         59 . The structure of  claim 58  wherein the roughness is less than 1 angstrom root-mean-square in a scan area of 1 μm×1 μm. 
     
     
         60 . The structure of  claim 53  wherein the semiconductor top surface has a roughness of less than 5 angstroms root-mean-square in a scan area of 40 μm×40 μm and a contamination level of less than 0.08 particles/cm 2 , the particles having a diameter greater than 0.2 micrometers. 
     
     
         61 . The structure of  claim 60  wherein the roughness is less than 1 angstrom root-mean-square in a scan area of 1 μm×1 μm. 
     
     
         62 . The structure of  claim 53  wherein the semiconductor layer top surface has a roughness of less than 5 angstroms root-mean-square in a scan area of 40 μm×40 μm and a contamination level of less than 0.019 particles/cm 2 , the particles having a diameter greater than 1 micrometer. 
     
     
         63 . The structure of  claim 62  wherein the roughness is less than 1 angstrom root-mean-square in a scan area of 1 μm×1 μm. 
     
     
         64 . The structure of  claim 53  wherein the semiconductor layer top surface has a roughness of less than 0.5 angstroms root-mean-square in a scan area of 1 μm×1 μm and a contamination level of less than 0.09 particles/cm 2 , the particles having a diameter greater than 0.09 micrometers. 
     
     
         65 . A semiconductor structure comprising:
 a substrate;   a semiconductor layer disposed over the substrate, the semiconductor layer including at least two elements; and   a regrowth layer disposed over the semiconductor layer, the regrowth layer having a top surface,   wherein the regrowth layer top surface is substantially haze-free.   
     
     
         66 . The structure of  claim 65  wherein the regrowth layer comprises a semiconductor material. 
     
     
         67 . The structure of  claim 66  wherein the regrowth layer comprises silicon. 
     
     
         68 . The structure of  claim 65  wherein the regrowth layer is strained. 
     
     
         69 . The structure of  claim 65  wherein a portion of the regrowth layer disposed below the regrowth layer top surface comprises a superlattice. 
     
     
         70 . A semiconductor structure comprising:
 a wafer, and   a semiconductor layer bonded to the wafer, the semiconductor layer having a top surface,   wherein the semiconductor layer top surface is substantially haze-free.   
     
     
         71 . The structure of  claim 70  wherein the semiconductor layer comprises silicon. 
     
     
         72 . The structure of  claim 70  wherein the semiconductor layer is strained. 
     
     
         73 . The structure of  claim 70  wherein the semiconductor layer comprises germanium. 
     
     
         74 . The structure of  claim 70  wherein the wafer comprises an insulating layer. 
     
     
         75 . The structure of  claim 74  wherein the insulating layer comprises silicon dioxide.