Semiconductor device package diepad having features formed by electroplating
Abstract
Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package.
Claims
exact text as granted — not AI-modified1 - 28 . (canceled)
29 . A semiconductor device package comprising:
a die; a plurality of pins formed by electroplating and configured to be in electrical communication with corresponding contacts on the die through respective solder connections; and an encapsulant in which the die, the internal solder connections, and the portions are embedded.
30 . The semiconductor device package of claim 29 wherein the pins are formed from copper.
31 . The semiconductor device package of claim 29 wherein the solder connections comprise solder balls.
32 . The semiconductor device package of claim 29 wherein the portions are raised relative to other portions of the pins that are in contact with the solder connections.
33 . The semiconductor device package of claim 32 wherein the raised portions extend toward an external surface of the encapsulant.
34 . The semiconductor device package of claim 32 wherein the portions comprise a different metal than the other portions.
35 . The semiconductor device package of claim 32 wherein the portions comprise a same metal as the other portions.
36 . The semiconductor device package of claim 32 further comprising an additional electroplated layer formed on the portions and extending to an external surface of the encapsulant.
37 . The semiconductor device package of claim 29 comprising a Chip Scale Package (CSP).
38 . A method for forming a semiconductor device package, the method comprising:
forming a plurality of pins having raised portions by electroplating; providing solder connections between the plurality of pins and corresponding contacts on a die; and encapsulating the raised portions, the die, and the solder connections within a plastic package body.
39 . The method of claim 38 wherein the electroplating comprises electroplating copper.
40 . The method of claim 38 wherein the electroplating comprises electroplating other than copper.
41 . The method of claim 38 wherein the plurality of pins are formed by electroplating selected regions of a metal sheet.
42 . The method of claim 38 wherein the plurality of pins are formed by electroplating selected regions of a metal sheet.
43 . The method of claim 42 wherein the electroplating of selected regions comprises electroplating selected regions exposed by a photoresist mask.
44 . The method of claim 42 wherein the metal sheet comprises copper.
45 . The method of claim 44 wherein the electroplated material comprises copper.
46 . The method of claim 44 wherein the electroplated material comprises other than copper.
47 . A method of manufacturing a semiconductor device package, the method comprising:
providing a die including a surface having contact pads; providing a plurality of pins having broad portions and raised portions formed by electroplating; creating solder connections between the plurality of pins and corresponding pads on the die; and embedding the die, solder connections, and broad pin portions within an encapsulant.
48 . The method of claim 47 wherein the raised portions are formed by electroplating selective areas of a metal sheet exposed by a photoresist mask.
49 . The method of claim 47 wherein the broad portions are formed by electroplating over metal present in an open area of a photoresist mask.Cited by (0)
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