Wafer level package with good cte performance

Abstract

The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the redistribution built up layer. Terminal Conductive bumps are coupled to the UBM.

1 . A structure of package comprising:
 a substrate with a pre-formed die receiving cavity and/or terminal contact pads formed within an upper surface of said substrate;   a die disposed within said die receiving cavity by adhesion;   a dielectric layer formed on said die and said substrate and refill into a gap between said die and said substrate to absorb thermal mechanical stress there between, wherein said dielectric layer includes an elastic dielectric layer, a photosensitive layer, a silicone dielectric based layer, a siloxane polymer (SINR) layer, a polyimides (PI) layer or silicone resin layer,   a re-distribution layer (RDL) formed on said dielectric layer and coupled to said die; and   pluralities of pads coupled to said RDL.   
     
     
         2 . The structure of  claim 1 , further comprising a conductive bump coupled to said pad. 
     
     
         3 . The structure of  claim 1 , wherein said RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy. 
     
     
         4 . The structure of  claim 1 , wherein the material of said substrate includes epoxy type FR5 or FR4. 
     
     
         5 . The structure of  claim 1 , wherein the material of said substrate includes BT, silicon, PCB (print circuit board) material, glass or ceramic. 
     
     
         6 . The structure of  claim 1 , wherein the material of said substrate includes alloy or metal. 
     
     
         7 . The structure of  claim 6 , wherein the material of said substrate includes Alloy42 (42% Ni-58% Fe) or Kovar (29% Ni-17% Co-54% Fe). 
     
     
         8 . The structure of  claim 1 , further includes a protection layer formed on said RDL. 
     
     
         9 . A method for forming semiconductor device package comprising:
 providing a substrate with a pre-formed die receiving cavity and/or terminal contact pads formed within an upper surface of said substrate;   using a pick and place fine alignment system to re-distribute known good dice on a carrier tool with desired pitch, wherein said carrier tool includes adhesive material at the periphery area of said carrier tool to adhere said substrate;   attaching adhesive material on die back side;   bonding said substrate on to said die back side, and curing then separating said tool from said substrate;   coating a dielectric layer on said die and substrate, followed by performing vacuum procedure;   forming an opening to expose a contact pad of said die and/or substrate;   forming at least one conductive built up layer over said dielectric layer;   forming a contacting structure over said at least one conductive built up layer;   forming a protection layer over said at least one conductive built up layer.   
     
     
         10 . The method of  claim 9 , further comprising forming a conductive bump coupled to said contacting structure. 
     
     
         11 . The method of  claim 9 , wherein said dielectric layer includes an elastic dielectric layer, a photosensitive layer, a silicone dielectric based material layer, a polyimides (PI) layer or a silicone resin layer. 
     
     
         12 . The method of  claim 11 , wherein said silicone dielectric based material comprises siloxane polymers (SINR), Dow Corning WL5000 series, or the combination thereof. 
     
     
         13 . The method of  claim 9 , wherein said at least one conductive built up layer is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy. 
     
     
         14 . The method of  claim 9 , wherein the material of said substrate includes epoxy type FR5 or FR4. 
     
     
         15 . The method of  claim 9 , wherein the material of said substrate includes BT, silicon, PCB (print circuit board) material, glass or ceramic. 
     
     
         16 . The method of  claim 9 , wherein the material of said substrate includes alloy or metal. 
     
     
         17 . The method of  claim 16 , wherein the material of said substrate includes Alloy42 (42% Ni-58% Fe) or Kovar (29% Ni-17% Co-54% Fe). 
     
     
         18 . The method of  claim 9 , wherein said carrier tool is made of glass.