Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device

Abstract

A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

1 . A metal-oxide-semiconductor transistor device, comprising:
 a semiconductor substrate;   an electrode on the semiconductor substrate;   a drain/source region in the semiconductor substrate beside the electrode;   a material layer on the surface or the top of the drain/source region and the electrode;   a protective layer on the material layer; and   a contact etch stop layer covering the electrode and the drain/source region.   
   
   
       2 . The metal-oxide-semiconductor transistor device of  claim 1 , wherein the protective layer comprises silicon oxide or silicon nitride. 
   
   
       3 . The metal-oxide-semiconductor transistor device of  claim 1 , wherein the material layer comprises metal silicide. 
   
   
       4 . The metal-oxide-semiconductor transistor device of  claim 3 , wherein the metal silicide comprises nickel silicide. 
   
   
       5 . The metal-oxide-semiconductor transistor device of  claim 1 , further comprising a liner on the sidewall of the electrode. 
   
   
       6 . The metal-oxide-semiconductor transistor device of  claim 1 , further comprising:
 an organic polymer layer on the sidewall of the electrode, the protective layer with the remained thickness, or the material layer.   
   
   
       7 . The metal-oxide-semiconductor transistor device of  claim 1 , wherein the contact etch stop layer is stressed. 
   
   
       8 . The metal-oxide-semiconductor transistor device of  claim 1 , further comprising:
 an interlayer dielectric layer covering the contact etch stop layer; and   a contact hole through the interlayer dielectric layer, the contact etch stop layer, and the protective layer to the drain/source region.