Method and apparatus to implement a reset function in a non-volatile static random access memory

Abstract

A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's.

1 . A method for resetting a semiconductor memory array having a plurality of semiconductor memory cells, each semiconductor memory cell having at least an SRAM cell having a bit line pair with a first bit line and a second bit line, said first bit lines of each semiconductor memory in a column of said array coupled together and second bit lines of each semiconductor memory in a column of said array coupled together, said method comprising:
 grounding a node supplying power to each of said SRAM cells by connecting said power supply node to a ground node for each of said SRAM cells, said ground node having a means for limiting current flowing through said ground node coupled to said SRAM cell ground node and a main ground node, said means for limiting current set to a predetermined current limit;   grounding said first bit line of said bit line pair independent of said second bit line of said bit line pair in each of said columns in an array using an array reset circuit, each SRAM cell in said column of said semiconductor memory array connected to a single array reset circuit configured to both ground and apply voltage to said first bit line independent of said second bit line;   applying a voltage representing a high state to each of said second bit lines of said bit line pairs in said semiconductor memory array;   applying a voltage representing a high state to said word line coupled to said SRAM cell; and   disconnecting said supply node from said ground node for each of said SRAM cells and applying a voltage representing a high state to said supply node thereby removing the current limit between said node supplying power and said SRAM cell ground node.   
   
   
       2 . The method of  claim 1 , further comprising grounding said word lines. 
   
   
       3 . The method of  claim 1 , wherein said semiconductor memory cell comprises a SRAM cell and a non-volatile portion, wherein said SRAM cell is coupled to said non-volatile portion for the transfer of a bit of data there between. 
   
   
       4 . The method of  claim 3 , wherein said non-volatile portion comprises a dual trigate transistor each having a nonvolatile eraseable programable memory transistor for storing said bit of data. 
   
   
       5 . The method of  claim 4 , wherein said SRAM cell comprises a six transistor SRAM. 
   
   
       6 . The method of  claim 1 , wherein said step of grounding the power supply node comprises clamping the node supplying power to said plurality of SRAM cells to the ground node for said plurality of SRAM cells. 
   
   
       7 . The method of  claim 6 , wherein said node supplying power is V CCI  and said ground node for said plurality of SRAM cells is V SSI , wherein said ground node is coupled to a means for limiting current through V SSI . 
   
   
       8 . A method for resetting a semiconductor memory cell having an SRAM cell, said SRAM cell having a bit line pair with a first bit line and a second bit line, said method comprising:
 grounding a node supplying power to each of said SRAM cells by connecting said power supply node to a ground node for each of said SRAM cells, said ground node having a means for limiting current flowing through said ground node coupled to said SRAM cell ground node and a main ground node, said means for limiting current set to a predetermined current limit;   grounding said first bit line of said bit line pair independent of said second bit line of said bit line pair in each of said columns in said array using an array reset circuit, each SRAM cell in said column of said semiconductor memory array connected to a single array reset circuit configured to both ground and apply voltage to said first bit line independent of said second bit line;   applying a voltage representing a high state to each of said second bit lines of said bit line pairs in said semiconductor memory array;   applying a voltage representing a high state to said word line coupled to said SRAM cell; and   disconnecting said supply node from said ground node for each of said SRAM cells and applying a voltage representing a high state to said supply node thereby removing the current limit between said node supplying power and said SRAM cell ground node.   
   
   
       9 . A semiconductor memory reset comprising:
 a memory cell having a volatile cell and a non-volatile cell, said non-volatile cell coupled to said volatile cell to transmit a bit of data there between, said volatile cell configured to receive a bit of data from an exterior source, retain a bit of data and transmit a bit of data to said exterior source, said volatile cell loses a retained bit of data when power is removed from said volatile cell, said non-volatile cell comprises a first and second transistor trigate each coupled to said volatile cell, each trigate having a store transistor, a recall transistor and a memory transistor, one transistor trigate being an erase trigate and one transistor trigate being a store trigate, said store transistors configured for connecting and disconnecting said non-volatile cell from said volatile cell, said recall transistors configured for connecting and disconnecting said non-volatile cell from a power source, said memory transistors configured for storing a bit of data received from said volatile cell and transmitting a bit of data to said volatile memory cell,   a current limiting means coupled to a ground node of said memory cell, said current limiting means configured for limiting the flow of current from said volatile memory cell to said memory ground node; and   an array reset circuit coupled to a bit line pair of said volatile memory, said array reset configured for independently controlling a voltage applied to each bit line in said bit line pair.   
   
   
       10 . The memory reset of  claim 9 , further comprising an array of memory cells having m-columns and n-rows, wherein each bit line pair of each memory cell in said m-columns is coupled to an array reset circuit. 
   
   
       11 . The memory reset of  claim 10 , wherein each of said memory cells in said array has a current limiting means coupled between said memory cell ground and a chip ground. 
   
   
       12 . The memory reset of  claim 11 , wherein said array circuit further comprises a first circuit portion and a second circuit portion, said first circuit portion having a first node for applying a high and a low state and at least one circuit component coupled to said first node for providing a current load to said bit line pair for independently pulling current into each bit line of said bit line pair, said second circuit portion having a first node for applying a high and a low state and at least one circuit component coupled to said first node and a second node for independently grounding each bit line of said bit line pair. 
   
   
       13 . The memory reset of  claim 12 , where said first circuit portion is a plurality of series connected p-channel transistors, wherein each gate of said plurality is coupled to said first node, wherein said source of at least one p-channel transistor is coupled to one bit line of said bit line pair and the drain of at least one p-channel transistor is coupled to a power source. 
   
   
       14 . The memory reset of  claim 13 , wherein said second circuit portion is at least one n-channel transistor, said gate of said n-channel transistor coupled to said first node, said drain of said n-channel transistor to one bit line of said bit line pair and said source of said n-channel transistor coupled to said ground node. 
   
   
       15 . The memory reset of  claim 14 , wherein said current limiting means is coupled between said memory ground node and a chip ground node. 
   
   
       16 . The memory reset of  claim 15 , wherein said current limiting means further comprises a current limiting transistor, wherein a gate of said current limiting transistor is coupled to a device for inputting a current limiting voltage, said source of said current limiting transistor is coupled to said chip ground node and said drain of said current limiting transistor is coupled to said memory ground node.