US2008174013A1PendingUtilityA1

Semiconductor device package and manufacturing method thereof

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Assignee: YANG JUN YOUNGPriority: Jan 5, 2005Filed: Feb 27, 2008Published: Jul 24, 2008
Est. expiryJan 5, 2025(expired)· nominal 20-yr term from priority
H10W 42/284H10W 42/276H10W 74/00H10W 72/0198H10W 90/754H10W 74/014H10W 74/121H10W 74/114H10W 74/40H10W 42/20
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Claims

Abstract

A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper of the substrate; and an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device. The present invention further provides methods for manufacturing the semiconductor device package.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device package comprising:
 a substrate;   a semiconductor device mounted and electrically coupled to the substrate;   a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and   an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device,   wherein the electromagnetic interference shielding layer is a layer of conductive paint in contact with the package body.   
   
   
       2 . The semiconductor device package as claimed in  claim 1 , further comprising at least one ground trace extending on the upper surface of the substrate and the conductive paint layer is connected to the ground trace. 
   
   
       3 . The semiconductor device package as claimed in  claim 1 , wherein the conductive paint layer has a main body and a side wall extending from the main body, and the bottom of the side wall is flush with a lower surface of the substrate. 
   
   
       4 . A semiconductor device package comprising:
 a substrate;   a semiconductor device mounted and electrically coupled to the substrate;   a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and   an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device,   wherein the electromagnetic interference shielding layer is an electroless plated metal layer in contact with the package body.   
   
   
       5 . The semiconductor device package as claimed in  claim 4 , further comprising at least one ground trace extending on the upper surface of the substrate and the electroless plated metal layer is connected to the ground trace. 
   
   
       6 . The semiconductor device package as claimed in  claim 4 , wherein the electroless plated metal layer has a main body and a side wall extending from the main body, and the bottom of the side wall is flush with a lower surface of the substrate. 
   
   
       7 . A semiconductor device package comprising:
 a substrate;   a semiconductor device mounted and electrically coupled to the substrate;   a package body encapsulating the semiconductor device against a portion of an Lpper surface of the substrate; and   an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device,   wherein the electromagnetic interference shielding layer is a metal cover securely attached to the package body via an adhesive layer.   
   
   
       8 . The semiconductor device package as claimed in  claim 7 , further comprising at least one ground trace extending on the upper surface of the substrate and the metal cover is connected to the ground trace. 
   
   
       9 . The semiconductor device package as claimed in  claim 7 , wherein the metal cover has a main body and a side wall extending from the main body, and the bottom of the side wall is flush with a lower surface of the substrate. 
   
   
       10 . A semiconductor device package comprising:
 a substrate;   a semiconductor device mounted and electrically coupled to the substrate;   a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate;   an electromagnetic interference shielding layer formed over the package body and substantially enclosing the semiconductor device; and   at least one ground trace extending on the upper surface of the substrate and the shielding layer is connected to the ground trace.

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