US2008197495A1PendingUtilityA1
Structure for reducing lateral fringe capacitance in semiconductor devices
Est. expiryMay 25, 2026(expired)· nominal 20-yr term from priority
Inventors:Lawrence A. ClevengerStephan GrunowKaushik A. KumarKevin S. PetrarcaVidhya RamachandranTheodorus E. Standaert
H10W 20/495H10W 20/47H10W 20/056H10W 20/093H10W 20/077
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Claims
Abstract
A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.
Claims
exact text as granted — not AI-modified1 . A semiconductor structure, comprising:
a plurality of conductive lines formed within an interlevel dielectric (ILD) layer; and a non-planar cap layer formed over said ILD layer and said conductive lines, wherein said cap layer is raised with respect to said conductive lines at locations between said conductive lines.
2 . The semiconductor structure of claim 1 , wherein said cap layer has a domed shape at said locations between said conductive lines.
3 . The semiconductor structure of claim 1 , wherein said ILD layer comprises silicon dioxide and said cap layer comprises nitrogen-doped silicon carbide.Join the waitlist — get patent alerts
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