Quad flat no-lead chip carrier with stand-off

Abstract

A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved.

1 . A chip carrier, comprising:
 a plate of material having a first surface having a chip attach region for attaching a chip to said carrier and another region around said chip attach region having a plurality of conductive leads for connecting to pads on said chip, said plate of material further having a second surface with an array of rounded conductive plate protrusions extending from said second surface.   
     
     
         2 . The chip carrier as set forth in  claim 1  wherein said chip carrier is a no-lead chip carrier with chip attached to said chip attach region. 
     
     
         3 . The chip carrier as set forth in  claim 1  wherein said protrusions extend from said second surface beneath at least said another region. 
     
     
         4 . The chip carrier as set forth in  claim 3  wherein said protrusions extend beneath said another region and said chip attach region. 
     
     
         5 . The chip carrier as set forth in  claim 1  wherein said plate of material is a plate of conductive material having a first surface with a chip attach region surrounded by a plurality of conductive lead regions and a second surface having an array of rounded protrusions of conductive material extending therefrom formed from said plate of conductive material. 
     
     
         6 . The chip carrier as set forth in  claim 5  wherein said rounded protrusions of conductive material extend from beneath at least said conductive lead regions. 
     
     
         7 . The chip carrier as set forth in  claim 6  wherein said array of rounded protrusions are each formed as a result of an array of opposing dimples formed in said first surface. 
     
     
         8 . The chip carrier as set forth in  claim 6  including a chip attached to said chip attach region and wire connections between said chip and said conductive lead regions. 
     
     
         9 . The chip carrier as set forth in  claim 8  wherein said conductive lead regions are respectively soldered to conductive pads on a printed circuit board. 
     
     
         10 . A method of forming an electronic package, comprising:
 forming a pattern in a plate of material including a chip attach region and conductive lead regions around said chip attach region for connecting a chip to said conductive lead regions on one surface of said plate of material; and   forming an array of conductive protrusions extending from said plate of material on a surface opposing said one surface, said protrusions extending from the plane of said surface opposing said one surface to provide both increased surface area for solder contact and solder joint stand-off height.   
     
     
         11 - 20 . (canceled) 
     
     
         21 . A method of forming an electronic package, comprising:
 forming a pattern in a plate of material to create a chip attach region and conductive lead regions around said chip attach region for connecting a chip to said conductive lead regions on one surface of said plate of material;   forming an array of conductive protrusions extending from a surface of said plate of material opposing said one surface, said protrusions extending from the plane of said surface opposing said one surface to provide increased surface area for increased surface area for solder contact and solder joint stand-off height beneath said conductive lead regions;   attaching a chip to said chip attach region on said one surface of said plate of material and forming conductive connections from said chip to said conductive lead regions on said one surface of said plate of material; and   encapsulating said chip and plate of material including said conductive lead regions on said one surface of said plate of material leaving said surface opposing said one surface and said array of conductive protrusions extending therefrom free of encapsulation.   
     
     
         22 . The method of  claim 21  including the step of plating said surface opposing said one surface and having said array of conductive protrusions extending therefrom with a layer of conductive material. 
     
     
         23 . The method of  claim 21  including the step of forming on said surface opposing said one surface and having said array of conductive protrusions extending therefrom a layer of solder. 
     
     
         24 . The method of  claim 23  including the step of:
 forming a layer of solder over electrical connecting surfaces of a substrate;   positioning said surface opposing said one surface and having said array of conductive protrusions extending therefrom in said layer of solder; and   reflowing the layers of solder.   
     
     
         25 . The method as set forth in  claim 24  wherein said protrusions are rounded protrusions formed by stamping dimples into said one surface.