Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays

Abstract

A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_w 1 and write_w 1 signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_w 1 signal and an output for outputting a delayed version of the write_w 1 signal. The wordline signal is activated by the wordline decoder based on the read_w 1 signal and the delayed write_w 1 signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.

1 . A memory system, comprising:
 a plurality of semiconductor memory cells;   a wordline decoder coupled to the memory cells through a plurality of wordlines, wherein the wordline decoder provides a wordline signal to at least one of the memory cells over at least one of the wordlines to allow access to the at least one memory cell for a read operation or a write operation, wherein the wordline decoder generates a read_w 1  signal based on whether a read operation is to be performed in the next cycle and generates a write_w 1  signal based on whether a write operation is to be performed in the next cycle, wherein the wordline decoder includes a buffer having an input for receiving the write_w 1  signal and an output for outputting a delayed version of the write_w 1  signal, and wherein the wordline decoder activates the wordline signal based on the read_w 1  signal and the delayed write_w 1  signal.   
   
   
       2 . The memory system as recited in  claim 1 , wherein the memory system is a domino static random access memory (SRAM) and the memory cells are SRAM cells. 
   
   
       3 . The memory system as recited in  claim 1 , wherein the buffer includes at least two inverters connected in series. 
   
   
       4 . The memory system as recited in  claim 1 , wherein the buffer includes a safety bit logic element to lengthen the delay in response to a value of a delay lengthening select signal. 
   
   
       5 . The memory system as recited in  claim 1 , wherein the wordline decoder further comprises:
 a first AND gate having inputs for receiving the read_w 1  signal, a first address bit signal, and a second address bit signal;   a second buffer having an input for receiving the first address bit signal and an output for outputting a delayed version of the first address bit signal;   a third buffer having an input for receiving the second address bit signal and an output for outputting a delayed version of the second address signal;   a second AND gate having inputs for receiving the delayed write_w 1  signal, the delayed first address bit signal, and the delayed second address bit signal;   an OR gate having inputs for receiving the output of the first AND gate and the output of the second AND gate.   
   
   
       6 . The memory system as recited in  claim 5 , wherein the wordline decoder activates the wordline signal based on the output of the OR gate. 
   
   
       7 . The memory system as recited in  claim 1 , wherein the wordline decoder further comprises a flip-flop latch having a first input for receiving a clock signal and a second input for receiving a read_writebar signal indicative of whether a read operation or a write operation is to be performed in the next clock cycle, as well as a first output for outputting the read_w 1  signal and a second output for outputting the write_w 1  signal. 
   
   
       8 . A data processing system, comprising:
 a processor;   a memory coupled via a bus to the processor;   a domino static random access memory (SRAM) located within one of the processor or the memory, the domino SRAM comprising
 a plurality of SRAM cells, 
 a wordline decoder coupled to the SRAM cells through a plurality of wordlines, wherein the wordline decoder provides a wordline signal to at least one of the SRAM cells over at least one of the wordlines to allow access to the at least one SRAM cell for a read operation or a write operation, wherein the wordline decoder generates a read_w 1  signal based on whether a read operation is to be performed in the next cycle and generates a write_w 1  signal based on whether a write operation is to be performed in the next cycle, wherein the wordline decoder includes a buffer having an input for receiving the write_w 1  signal and an output for outputting a delayed version of the write_w 1  signal, and wherein the wordline decoder activates the wordline signal based on the read_w 1  signal and the delayed write_w 1  signal. 
   
   
   
       9 . The data processing system as recited in  claim 8 , wherein the processor includes a cache, and wherein the domino SRAM is located within the processor's cache. 
   
   
       10 . The data processing system as recited in  claim 8 , wherein the buffer includes at least two inverters connected in series. 
   
   
       11 . The data processing system as recited in  claim 8 , wherein the buffer includes a safety bit logic element to lengthen the delay in response to a value of a delay lengthening select signal. 
   
   
       12 . The data processing system as recited in  claim 8 , wherein the wordline decoder further comprises:
 a first AND gate having inputs for receiving the read_w 1  signal, a first address bit signal, and a second address bit signal;   a second buffer having an input for receiving the first address bit signal and an output for outputting a delayed version of the first address bit signal;   a third buffer having an input for receiving the second address bit signal and an output for outputting a delayed version of the second address signal;   a second AND gate having inputs for receiving the delayed write_w 1  signal, the delayed first address bit signal, and the delayed second address bit signal;   an OR gate having inputs for receiving the output of the first AND gate and the output of the second AND gate.   
   
   
       13 . The data processing system as recited in  claim 12 , wherein the wordline decoder activates the wordline signal based on the output of the OR gate. 
   
   
       14 . The data processing system as recited in  claim 8 , wherein the wordline decoder further comprises a flip-flop latch having a first input for receiving a clock signal and a second input for receiving a read_writebar signal indicative of whether a read operation or a write operation is to be performed in the next clock cycle, as well as a first output for outputting the read_w 1  signal and a second output for outputting the write_w 1  signal. 
   
   
       15 . A computer program product for implementing a domino static random access memory (SRAM) in a digital computing device having at least one processor, comprising:
 a plurality of executable instructions provided on computer readable signal bearing media, wherein the executable instructions, when executed by the at least one processor, cause the digital computing device to perform the steps of:   (a) generating a read_w 1  signal based on whether a read operation is to be performed in the next cycle;   (b) generating a write_w 1  signal based on whether a write operation is to be performed in the next cycle;   (c) determining a write operation timing requirement;   (d) generating a delay lengthening select signal based on the determined write operation timing requirement;   (e) varying a delay applied to the write_w 1  signal in response to a value of the delay lengthening select signal;   (f) activating a wordline signal based on the read_w 1  signal and the delayed write_w 1  signal and providing the wordline signal to at least one SRAM cell to allow access to the at least one SRAM cell for a read operation or a write operation.   
   
   
       16 . The computer program product as recited in  claim 15 , wherein the signal bearing media comprises recordable media. 
   
   
       17 . The computer program product as recited in  claim 15 , wherein the signal bearing media comprises transmission media. 
   
   
       18 . A domino static random access memory (SRAM) array, comprising:
 a plurality of SRAM cells;   a wordline decoder coupled to the SRAM cells through a plurality of wordlines, wherein the wordline decoder provides a wordline signal to at least one of the SRAM cells over at least one of the wordlines to allow access to the at least one SRAM cell for a read operation or a write operation, wherein the wordline decoder generates a first signal based on whether a read operation is to be performed in the next cycle and generates a second signal based on whether a write operation is to be performed in the next cycle, wherein the wordline decoder includes a delay mechanism that delays the second signal relative to the first signal, and wherein the wordline decoder activates the wordline signal based on the first signal and the delayed second signal.   
   
   
       19 . A domino SRAM array as recited in  claim 18 , wherein the delay mechanism outputs the delayed second signal by applying a fixed delay to the second signal. 
   
   
       20 . A domino SRAM array as recited in  claim 18 , wherein the delay mechanism outputs the delayed second signal by applying an adjustable delay to the second signal.