Semiconductor Package and Method for Fabricating the Same

Abstract

A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip in the semiconductor package. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. The central electrode pads and the conductor plate may also be connected together using gold stud bumps. Preferably, the conductor plate is composed of a multilayer structure of two or more layers, and each conductor plate is used in power-supply wiring or ground wiring.

1 . A semiconductor package comprising:
 a wiring substrate having a power-supply wiring pad;   a semiconductor chip disposed on the wiring substrate and having a plurality of peripheral electrode pads and at least one central electrode pad on a principal surface thereof, the plurality of peripheral electrode pads being connected to the wiring substrate, the central electrode pad being disposed so as to be surrounded by the peripheral electrode pads and receiving power supplied from the wiring substrate; and   at least one conductor disposed on the semiconductor chip and electrically connected to the central electrode pad, the conductor having at least one extraction portion connected to the power-supply wiring pad of the wiring substrate.   
     
     
         2 . The semiconductor package according to  claim 1 , further comprising an insulating layer,
 wherein the conductor is a conductor plate, and the conductor plate is disposed on the semiconductor chip such that the insulating layer is disposed therebetween.   
     
     
         3 . The semiconductor package according to  claim 1 , wherein the plurality of peripheral electrode pads are electrically connected to the wiring substrate using bonding wires. 
     
     
         4 . The semiconductor package according to  claim 2 , wherein the insulating layer comprises one of a nonconductive film and a nonconductive paste. 
     
     
         5 . The semiconductor package according to  claim 1 , wherein the wiring substrate is a ball grid array (BGA) substrate constituting an interposer substrate connected to an external circuit. 
     
     
         6 . The semiconductor package according to  claim 2 , wherein the conductor plate and the insulating layer have at least one opening at a position corresponding to the central electrode pad, and the conductor plate is electrically connected to the central electrode pad through the opening using a bonding wire. 
     
     
         7 . The semiconductor package according to  claim 6 , wherein the at least one opening comprises a plurality of openings arranged in a grid. 
     
     
         8 . The semiconductor package according to  claim 2 , wherein the insulating layer comprises one of an anisotropic conductive film and a nonconductive paste, and the conductor plate is electrically connected to the central electrode pad using a stud bump. 
     
     
         9 . The semiconductor package according to  claim 2 , wherein the conductor plate is used in at least one of ground wiring and power-supply wiring. 
     
     
         10 . The semiconductor package according to  claim 2 , wherein the conductor plate is made of a metal and is subjected to surface treatment of metal plating. 
     
     
         11 . The semiconductor package according to  claim 2 , further comprising:
 a second insulating layer disposed on the conductor plate; and   a second conductor plate disposed on the second insulating layer and having at least one second extraction portion connected to the power-supply wiring pad of the wiring substrate.   
     
     
         12 . The semiconductor package according to  claim 11 , wherein the second conductor plate is electrically connected to the central electrode pad on the semiconductor chip, and the second conductor plate is used in at least one of ground wiring and power-supply wiring. 
     
     
         13 . The semiconductor package according to  claim 11 , wherein the conductor plate, the second insulating layer, and the second conductor plate are integrally formed into a multilayer plate, and each of the conductor plate and the second conductor plate is used in at least one of power-supply wiring and ground wiring. 
     
     
         14 . The semiconductor package according to  claim 13 , wherein the multilayer plate has at least one extraction portion and an opening corresponding to the central electrode pad, and a surface of the conductor plate is exposed in accordance with an arrangement of the central electrode pad. 
     
     
         15 . A method for fabricating a semiconductor package, the method comprising the steps of:
 (a) preparing a wiring substrate having a power-supply wiring pad;   (b) preparing a semiconductor chip having a plurality of peripheral electrode pads and at least one central electrode pad on a principal surface thereof, the plurality of peripheral electrode pads being connected to the wiring substrate, the central electrode pad being disposed so as to be surrounded by the peripheral electrode pads and receiving power supplied from the wiring substrate;   (c) joining the semiconductor chip to the wiring substrate;   (d) preparing a conductor plate having at least one edge at a periphery thereof;   (e) forming an insulating layer on at least part of an upper surface of the semiconductor chip;   (f) disposing the conductor plate on the insulating layer;   (g) connecting the edge of the conductor plate to the power-supply wiring pad of the wiring substrate; and   (h) connecting at least part of the conductor plate except for the edge to the central electrode pad.   
     
     
         16 . The method according to  claim 15 , wherein the edge of the conductor plate is an extraction portion, the conductor plate and the insulating layer have an opening corresponding to the central electrode pad, and the at least part of the conductor plate is connected to the central electrode pad through the opening by wire bonding. 
     
     
         17 . The method according to  claim 15 , wherein the semiconductor chip has a gold stud bump on the central electrode pad, and the insulating layer comprises an anisotropic conductive film. 
     
     
         18 . The method according to  claim 15 , further comprising the steps of:
 preparing a second conductor plate having at least one second edge at a periphery thereof and an opening corresponding to the central electrode pad;   forming a second insulating layer on at least part of an upper surface of the conductor plate;   disposing the second conductor plate on the second insulating layer;   connecting the second edge to the power-supply wiring pad of the wiring substrate; and   connecting at least part of the second conductor plate except for the second edge to the central electrode pad.   
     
     
         19 . The method according to  claim 18 , wherein the second edge is a second extraction portion, the insulating layer has an opening corresponding to the conductor plate, the second insulating layer has an opening corresponding to the second conductor plate, and the at least part of the second conductor plate is connected to the central electrode pad through insulating layer opening and the second insulating layer opening by wire bonding. 
     
     
         20 . The method according to  claim 18 , wherein the conductor plate, the second insulating layer, and the second conductor plate are integrally formed into a multilayer plate, and the multilayer plate has at least one peripheral extraction portion and an opening corresponding to the central electrode pad.