Delay circuit and test apparatus

Abstract

There is provided a delay circuit that delays an input signal to output the delayed signal. The delay circuit includes a first delay element operable to receive the input signal and delay the input signal to output the delayed signal, a buffer operable to receive the delay signal output from the first delay element and correct a dullness of a waveform of the delay signal generated from the first delay element to output the corrected signal, and a second delay element operable to receive the delay signal output from the buffer and delay the delay signal to output the delayed signal.

1 . A delay circuit that delays an input signal to output the delayed signal, comprising:
 a first delay element operable to receive the input signal and delay the input signal to output the delayed signal;   a buffer operable to receive the delay signal output from said first delay element and correct a dullness of a waveform of the delay signal generated from said first delay element to output the corrected signal; and   a second delay element operable to receive the delay signal output from said buffer and delay the delay signal to output the delayed signal.   
   
   
       2 . The delay circuit as claimed in  claim 1 , wherein said first delay element and said second delay element are variable delay elements that respectively have a delay amount according to a delay setting data set previously, and said buffer is an element that has a substantially constant delay amount regardless of the delay setting data. 
   
   
       3 . The delay circuit as claimed in  claim 2 , wherein said first delay element has a first inverter that delays and inverts the input signal to output the delay signal, said second delay element has a second inverter that delays and inverts the delay signal to output the delay signal, and said buffer outputs the delay signal to said second delay element via two inverters connected serially. 
   
   
       4 . The delay circuit as claimed in  claim 3 , wherein said first delay element further has a first current source that controls a power source current through the first inverter to control the delay amount of the first inverter, said second delay element further has a second current source that controls a power source current through the second inverter to control the delay amount of the second inverter, and the delay circuit further comprises a delay control block operable to control the power source current generated from the first current source and the second current source. 
   
   
       5 . The delay circuit as claimed in  claim 4 , wherein said delay control block comprises:
 a voltage generating unit that generates a basic voltage according to a given delay setting data; and   a voltage converting unit that converts the basic voltage into a control voltage and supplies the control voltage to the first current source and the second current source, according to the characteristics of the first current source and the second current source, in order to cause the first current source and the second current source to generate the power source current.   
   
   
       6 .- 9 . (canceled)