Method for obtaining high-quality boundary for semiconductor devices fabricated on a partitioned substrate

Abstract

One embodiment of the present invention provides a process for obtaining high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate. During operation, the process receives a trench-partitioned substrate wherein the substrate surface is partitioned into arrays of isolated deposition platforms which are separated by arrays of trenches. The process then forms a multilayer structure, which comprises a first doped layer, an active layer, and a second doped layer, on one of the deposition platforms. Next, the process removes sidewalls of the multilayer structure.

1 . A method for obtaining high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate, comprising:
 receiving a trench-partitioned substrate wherein the substrate surface is partitioned into arrays of isolated deposition platforms which are separated by arrays of trenches;   forming a multilayer structure, which comprises a first doped layer, an active layer, and a second doped layer, on one of the deposition platforms; and   removing sidewalls of the multilayer structure.   
   
   
       2 . The method of  claim 1 , wherein removing the sidewalls of the multilayer structure involves etching the sidewalls using one of the following:
 a dry etching process;   a wet etching process; and   a combined dry etching and wet etching process.   
   
   
       3 . The method of  claim 2 , wherein prior to etching the sidewalls, the method further comprises protecting non-boundary surface of the multilayer structure with a mask layer, thereby only exposing the boundary region of the multilayer structure to the subsequent etching process. 
   
   
       4 . The method of  claim 3 , wherein the exposed boundary width is between 2 μm and 50 μm. 
   
   
       5 . The method of  claim 2 , wherein if a dry etching process is used, the method further comprises controlling the dry etching process to at least etch through the active layer of the multilayer structure, wherein the dry etching process is directed perpendicular to the multilayer structure. 
   
   
       6 . The method of  claim 2 , wherein the dry etching process is an inductively coupled plasma (ICP) etching. 
   
   
       7 . The method of  claim 2 , wherein the wet etching process involves using a H 3 PO 4  based etchant. 
   
   
       8 . The method of  claim 7 , wherein the method comprises heating the H 3 PO 4  based etchant to a temperature greater than 100° C. 
   
   
       9 . The method of  claim 2 , wherein the etching process is performed from the underside of the multiple structures, and wherein the method further comprises:
 bonding a supporting structure to the topside of the multiple structures;   removing the trench-partitioned substrate to expose the underside of the multiple structures, wherein the multilayer structures are attached to the supporting structure;   patterning the underside of the multiple structures to expose undesirable boundary regions of the multiple structures; and   removing the sidewalls of the multiple structures corresponding to the undesirable boundary region.   
   
   
       10 . The method of  claim 9 , wherein removing the sidewalls of the multiple structures involves using a H 3 PO 4  based etchant to wet-etch the sidewalls. 
   
   
       11 . The method of  claim 10 , wherein the method comprises heating the H 3 PO 4  based etchant to a temperature greater than 100° C. 
   
   
       12 . A semiconductor device obtained by a process for producing high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate, the process comprising:
 receiving a trench-partitioned substrate wherein the substrate surface is partitioned into arrays of isolated deposition platforms which are separated by arrays of trenches;   forming a multilayer structure, which comprises a first doped layer, an active layer, and a second doped layer, on one of the deposition platforms; and   removing sidewalls of the multilayer structure.   
   
   
       13 . The semiconductor device obtained by the process of  claim 12 , wherein removing the sidewalls of the multilayer structure involves etching the sidewalls using one of the following:
 a dry etching process;   a wet etching process; and   a combined dry etching and wet etching process.   
   
   
       14 . The semiconductor device obtained by the process of  claim 13 , wherein prior to etching the sidewalls, the process further comprises protecting non-boundary surface of the multilayer structure with a mask layer, thereby only exposing the boundary region of the multilayer structure to the subsequent etching process. 
   
   
       15 . The semiconductor device obtained by the process of  claim 14 , wherein the exposed boundary width is between 2 μm and 50 μm. 
   
   
       16 . The semiconductor device obtained by the process of  claim 13 , wherein if a dry etching process is used, the process further comprises controlling the dry etching process to at least etch through the active layer of the multilayer structure, wherein the dry etching process is directed perpendicular to the multilayer structure. 
   
   
       17 . The semiconductor device obtained by the process of  claim 13 , wherein the dry etching process is an inductively coupled plasma (ICP) etching. 
   
   
       18 . The semiconductor device obtained by the process of  claim 13 , wherein the wet etching process involves using a H 3 PO 4  based etchant, and wherein the process comprises heating the H 3 PO 4  based etchant to a temperature greater than 100° C. 
   
   
       19 . The semiconductor device obtained by the process of  claim 18 , wherein the process comprises heating the H 3 PO 4  based etchant to a temperature greater than 100° C. 
   
   
       20 . The semiconductor device obtained by the process of  claim 13 , wherein the etching process is performed from the underside of the multiple structures, and wherein the process further comprises:
 bonding a supporting structure to the topside of the multiple structures;   removing the trench-partitioned substrate to expose the underside of the multiple structures, wherein the multilayer structures are attached to the supporting structure;   patterning the underside of the multiple structures to expose undesirable boundary regions of the multiple structures; and   removing the sidewalls of the multiple structures corresponding to the undesirable boundary region.   
   
   
       21 . The semiconductor device obtained by the process of  claim 20 , wherein removing the sidewalls of the multiple structures involves using a H 3 PO 4  based etchant to wet-etch the sidewalls. 
   
   
       22 . The semiconductor device obtained by the process of  claim 21 , wherein the process comprises heating the H 3 PO 4  based etchant to a temperature greater than 100° C. 
   
   
       23 . A semiconductor device, comprising:
 a supporting substrate;   a multilayer structure, which comprises a bottom electrode, a first doped layer, an active layer, a second doped layer, and a top electrode, which is formed on the supporting substrate; and   a bonding layer between the supporting substrate and the multilayer structure, wherein the bonding layer holds the multilayer structure and the supporting substrate together;   wherein the multilayer structure has high-quality sidewalls which are obtained by removing original sidewalls of the multiple structures corresponding to an undesirable boundary region.