Semiconductor device including a planarized surface and method thereof

Abstract

A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.

1 - 13 . (canceled) 
   
   
       14 . A semiconductor device comprising:
 a base material layer having a depression region;   a medium material layer formed on the bottom of the depression region; and   a buried material layer formed on the medium material layer in the depression region, the buried material layer forming a surface co-planar with the surface of the base material layer.   
   
   
       15 . The semiconductor device of  claim 14 , wherein the buried material layer has a lower removal rate during chemical mechanical polishing than a removal rate of the medium material layer during chemical mechanical polishing. 
   
   
       16 . The semiconductor device of  claim 15 , further comprising an etch stop layer formed on the base material layer at an outer side of the depression region. 
   
   
       17 . The semiconductor device of  claim 16 , wherein the buried material layer forms a surface co-planar with the surface of the etch stop layer. 
   
   
       18 . The semiconductor device of  claim 16 , wherein the base material layer is a silicon substrate and the depression region is a trench region penetrating the base material layer. 
   
   
       19 . The semiconductor device of  claim 16 , wherein the base material layer is selected from the group consisting of an insulating material layer and a conductive material layer formed on a silicon substrate, and the depression region is a trench region penetrating the base material layer. 
   
   
       20 . The semiconductor device of  claim 18 , wherein the etch stop layer is a silicon nitride layer, and the buried material layer is an oxide layer. 
   
   
       21 . The semiconductor device of  claim 20 , wherein the oxide layer is selected from the group consisting of a PE-TEOS layer, an HDP oxide layer and a USG layer, and the medium material layer is a BPSG layer. 
   
   
       22 . A method for reducing the occurrence of a dishing phenomenon in a semiconductor device comprising:
 forming a depression region in a base material layer;   depositing a medium material layer on the base material layer;   depositing a buried material layer; and   planarizing until the medium material layer is removed and a planarized buried material layer is formed;   wherein the buried material layer has a lower removal rate during planarizing than a removal rate of the medium material layer during the planarizing.   
   
   
       23 . The method of  claim 22 , wherein said forming step comprises:
 forming an etch stop layer pattern on the base material layer; and   etching the base material layer using the etch stop layer pattern as an etch mask to form the depression region.   
   
   
       24 . The method of  claim 22 , wherein said performing step is performed until the etch stop layer pattern is exposed. 
   
   
       25 . The method of  claim 22 , further comprising selectively removing the medium material layer from the depression region before depositing the buried material layer. 
   
   
       26 . The method of  claim 22 , wherein the planarizing step includes chemical mechanical polishing. 
   
   
       27 . The method of  claim 26 , wherein the base material layer is a silicon substrate, the depression region is a trench region penetrating the base material layer, the etch stop layer pattern is a silicon nitride layer, and the buried material layer is an oxide layer. 
   
   
       28 . The method of  claim 27 , wherein the oxide layer is selected from the group consisting of a PE-TEOS layer, a USG layer and an HDP layer. 
   
   
       29 . The method of  claim 27 , further comprising flowing a slurry over the medium material layer and the buried material layer during the chemical mechanical polishing. 
   
   
       30 . The method of  claim 29 , wherein the slurry contains ammonium polycarboxylate (APC) as an additive. 
   
   
       31 . The method of  claim 30 , wherein the APC is added to the slurry in an amount of from approximately 2.0 to 4.5 parts by weight. 
   
   
       32 . The method of  claim 22 , further comprising forming at least one of a thermal oxide layer and a silicon liner layer in the depression region before depositing the buried material layer. 
   
   
       33 . A method of increasing a removal rate ratio of a medium material layer to a buried material layer comprising:
 adding a slurry including an anionic surfactant to a contact area on a semiconductor device;   adsorbing the anionic surfactant onto the surface of at least the buried material layer;   wherein the adsorbed anionic surfactant represses the removal rate of the buried material layer and increases the removal rate ratio of the medium material layer to the buried material layer.   
   
   
       34 . The method of  claim 33 , wherein the buried material layer is an oxide layer selected from the group consisting of a PE-TEOS layer, a USG layer and an HDP layer. 
   
   
       35 . The method of  claim 34 , wherein the medium material layer is a boron phosphorous silicate glass layer. 
   
   
       36 . The method of  claim 35 , wherein the removal rate ratio is a ratio of the removal rate of the medium material layer in a chemical mechanical polishing process to the removal rate of the buried material layer in a chemical mechanical polishing process. 
   
   
       37 . The method of  claim 33 , wherein the anionic surfactant is ammonium polycarboxylate. 
   
   
       38 . A method of planarizing the surface of a semiconductor device, the method comprising:
 etching a base material layer having an etch stop layer pattern to form a depression region on the base material layer;   forming a medium material layer on at least the etch stop layer pattern;   depositing a buried material layer on the medium material layer to fill the depression region;   removing the buried material layer until the surface of the medium material layer is exposed; and   planarizing the medium material layer and the buried material layer until the surface of the etch stop layer pattern is exposed to form a semiconductor device according to  claim 14 .   
   
   
       39 . A method for reducing the occurrence of a dishing phenomenon in a semiconductor device comprising:
 forming a depression region in a base material layer;   depositing a medium material layer on the base material layer;   depositing a buried material layer having a lower removal rate during planarizing than a removal rate of the medium material during the planarizing; and   planarizing until the medium layer is removed and a planarized buried material layer is formed to create a semiconductor device according to  claim 14 .