US2008296254A1PendingUtilityA1

Multilayer wiring board for an electronic device

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Assignee: TESSERA INTERCONNECT MATERIALSPriority: Jul 2, 2003Filed: Jan 11, 2008Published: Dec 4, 2008
Est. expiryJul 2, 2023(expired)· nominal 20-yr term from priority
H10W 90/401H10W 70/60H10W 70/09H05K 1/189H05K 1/182H05K 3/46H05K 2203/0384H05K 2201/0367H05K 3/4652H05K 3/4635H05K 3/4614H05K 3/205H05K 3/06H05K 1/187H05K 1/167H05K 1/165H05K 1/162H05K 1/16H05K 1/0393Y10T29/49155H05K 3/4007
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Claims

Abstract

To provide a multilayer wiring board mainly used for an electronic device, in which a bump passing through an inter layer insulating film allows for inter layer connection between plural wiring films insulated from one another with plural inter layer insulating layers. In the multilayer wiring board, a circuit element such as an electronic part, a semiconductor chip, or a passive element is accommodated in the inter layer insulating films so as to connect its terminal with the corresponding wiring film. In particular, the semiconductor chip is polished to a thickness of 50 μm or smaller, and the multilayer wiring board itself for the electronic device has the flexibility.

Claims

exact text as granted — not AI-modified
1 . A method of manufacturing a multilayer wiring board for an electronic device, comprising:
 preparing a first metal plate by forming a wiring film on a surface of a terminal bump formation metal layer;   preparing a semiconductor chip that is formed with a thickness of 50 mm or smaller;   preparing a second metal plate in which an inter layer connection bump connected to the wiring film on the first metal plate and a semiconductor chip accommodating space for accommodating the semiconductor chip are formed on one surface of a wiring film formation metal layer, and the inter layer connection bump passes through the surface, and an inter layer insulating film is laminated thereon outside the semiconductor chip accommodating space;   subjecting the semiconductor chip to flip-chip bonding to one surface of the first metal plate on a side where the wiring film is formed such that its electrode is connected with the wiring film;   laminating the second metal plate through the inter layer insulating film on the one surface of the first metal plate on the side where the wiring film is formed by connecting to the wiring film on the second metal plate a top surface of the inter layer connection bump exposed to the inter layer insulating film while the semiconductor chip is accommodated within the semiconductor chip accommodating space;   forming a wiring film by selectively etching the wiring film formation metal layer of the second metal plate; and   forming a terminal bump by selectively etching the terminal bump formation metal layer of the first metal plate.   
     
     
         2 . A method of manufacturing a multilayer wiring board for an electronic device, comprising:
 preparing a first metal layer constituting a wiring film where a passive element made from an element film is formed on its one surface;   preparing a second metal layer used as a base where bumps are selectively formed on its one surface by effecting one of selective etching and selective plating on a metal plate;   laminating the second metal layer on the first metal layer on a side where the element film is formed, through an inter layer insulating film such that the bumps pass through the inter layer insulating film to be connected with the first metal layer; and   forming a wiring film connected with a terminal of the passive element by selectively etching the first metal layer.   
     
     
         3 . A method of manufacturing a multilayer wiring board for an electronic device, comprising:
 preparing a metal layer constituting a wiring film where a passive element made from an element film is formed on its surface;   forming bumps each constituting an inter layer connection conductive layer by selectively etching a second metal layer of a laminate metal plate prepared by laminating a first metal layer and the second metal layer through a third metal layer serving as an etching stopper;   laminating an inter layer insulating film on a surface having the bumps formed thereon of the laminate metal plate such that the bumps pass through the inter layer insulating film;   polishing a surface of each of the bumps;   bonding, for lamination, the surface having the element film formed thereon of the metal layer to the surface of the laminate metal plate on which the inter layer insulating film is laminated such that the bumps are connected with the metal layer;   forming a wiring film connected with a terminal of the passive element by selectively etching the metal layer having the passive element formed thereon; and   forming a wiring film by selectively etching the first metal layer of the laminate metal plate.   
     
     
         4 . A method of manufacturing a multilayer wiring board for an electronic device according to  claim 2  or  3 , wherein the passive element comprises a resistor made from the element film formed by printing on the surface of the metal layer, carbon phenol or other low-temperature curing organic resins, followed by drying and curing. 
     
     
         5 . A method of manufacturing a multilayer wiring board for an electronic device according to  claim 2  or  3 , wherein the passive element comprises a resistor made from the element film formed by selectively applying ruthenium oxide or other high-temperature calcining inorganic thick paste to the surface of the metal layer and drying the resultant, followed by calcination in a reducing atmosphere furnace. 
     
     
         6 . A method of manufacturing a multilayer wiring board for an electronic device according to  claim 2  or  3 , wherein the passive element comprises a capacitor made from the element film formed by selectively applying to the surface of the metal layer a low-temperature curing organic resin mainly containing barium titanate, followed by drying and curing. 
     
     
         7 . A method of manufacturing a multilayer wiring board for an electronic device according to  claim 2  or  3 , wherein the passive element comprises a capacitor made from the element film formed by selectively applying a high-temperature calcining inorganic thick paste mainly containing barium titanate on the surface of the metal layer and drying the resultant, followed by calcination in a reducing atmosphere furnace.

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