Semiconductor Devices Including Doped Metal Silicide Patterns and Related Methods of Forming Such Devices

Abstract

Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.

1 . A method of forming a semiconductor device, the method comprising:
 forming an interlayer dielectric on a semiconductor substrate;   forming a contact hole in the interlayer dielectric that exposes a portion of the semiconductor substrate;   forming a metal pattern that includes a dopant in the contact hole on the exposed portion of the semiconductor substrate; and   performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern and to diffuse some of the dopant into the semiconductor substrate.   
   
   
       2 . The method of  claim 1 , wherein forming the metal pattern that includes the dopant comprises forming the metal pattern that includes the dopant using an electroless plating process. 
   
   
       3 . The method of  claim 1 , further comprising forming a metal contact in the contact hole after forming the metal pattern, wherein the heat treatment process is preformed before the metal contact is formed. 
   
   
       4 . The method of  claim 1 , further comprising forming a metal contact in the contact hole after forming the metal pattern, wherein the heat treatment process is performed after the metal contact is formed. 
   
   
       5 . The method of  claim 1 , wherein the semiconductor substrate comprises:
 a PMOS region that includes a first source/drain region, the PMOS region having a first gate pattern thereon; and   an NMOS region that includes a second source/drain region, the NMOS region having a second gate pattern thereon,   wherein the contact hole comprises a first contact hole that exposes the first source/drain region,   wherein the metal pattern comprises a first metal pattern that is formed through an electroless plating process,   and wherein the method further comprises forming a second contact hole in the interlayer dielectric that exposes the second source/drain region.   
   
   
       6 . The method of  claim 5 , wherein the first metal pattern comprises a first metal doped with boron (B). 
   
   
       7 . The method of  claim 6 , further comprising forming a first diffusion barrier pattern and a first metal contact in the first contact hole and forming a second diffusion barrier pattern and a second metal contact in the second contact hole. 
   
   
       8 . The method of  claim 7 , wherein the metal silicide pattern includes cobalt (Co), nickel (Ni), lead (Pd) and/or platinum (Pt) and is between the first source/drain region and the first metal contact; and
 wherein the method further comprises forming a titanium silicide pattern between the second source/drain region and the second metal contact.   
   
   
       9 . The method of  claim 7 , wherein the first metal pattern is also formed on the second source/drain region, and the metal silicide pattern is formed between the first source/drain region and the first metal contact, and between the second source/drain region and the second metal contact. 
   
   
       10 . The method of  claim 5 , further comprising forming a second metal pattern that includes phosphorus (P) on the exposed second source/drain region. 
   
   
       11 . The method of  claim 10 , further comprising forming a diffusion barrier pattern and a metal contact in each of the first and second contact holes. 
   
   
       12 . The method of  claim 11 , wherein the metal silicide pattern comprises:
 a first metal silicide pattern between the first source/drain region and the metal contact in the first contact hole; and   a second metal silicide pattern between the second source/drain region and the metal contact in the second contact hole.   
   
   
       13 . The method of  claim 11 , wherein the heat treatment process is performed after the metal contacts are formed. 
   
   
       14 . The method of  claim 11 , wherein the heat treatment process is performed before the diffusion barrier patterns are formed. 
   
   
       15 . A method of forming a semiconductor device, the method comprising:
 forming an interlayer dielectric on a silicon substrate;   forming a contact hole in the interlayer dielectric that exposes the silicon substrate;   selectively forming a metal pattern that includes a dopant in the contact hole; and   converting at least part of the metal pattern that includes the dopant into a metal silicide pattern; and   diffusing some of the dopant from the metal pattern into the silicon substrate.   
   
   
       16 . The method of  claim 15 , wherein the silicon substrate comprises a PMOS region that includes a first source/drain region and an NMOS region that includes a second source/drain region,
 wherein the contact hole comprises a first contact hole that exposes the first source/drain region,   wherein the metal pattern that includes the dopant comprises a first metal pattern that includes at least 1% boron (B) by atomic weight that is fonned through an electroless plating process,   and wherein the method further comprises forming a second contact hole in the interlayer dielectric that exposes the second source/drain region.   
   
   
       17 . The method of  claim 16 , wherein the metal silicide pattern includes cobalt (Co), nickel (Ni), lead (Pd) and/or platinum (Pt) and is between the first source/drain region and the first metal contact; and
 wherein the method further comprises forming a titanium silicide pattern between the second source/drain region and the second metal contact.   
   
   
       18 . A semiconductor device, comprising:
 a semiconductor substrate;   an interlayer dielectric on the semiconductor substrate;   a metal contact penetrating the interlayer dielectric to be electrically connected to the semiconductor substrate; and   a metal silicide pattern between the metal contact and the semiconductor substrate,   wherein the metal silicide pattern includes a dopant.   
   
   
       19 . The semiconductor device of  claim 18 , wherein the semiconductor substrate comprises:
 a PMOS region including a first gate pattern and a first source/drain region; and   an NMOS region including a second gate pattern and a second source/drain region,   wherein the metal contact comprises:   a first metal contact electrically connected to the first source/drain region; and   a second metal contact electrically connected to the second source/drain region.   
   
   
       20 . The semiconductor device of  claim 19 , wherein the metal silicide pattern is between the first source/drain region and the first metal contact. 
   
   
       21 . The semiconductor device of  claim 19 , wherein the metal silicide pattern is between the first source/drain region and the first metal contact and between the second source/drain region and the second metal contact. 
   
   
       22 . The semiconductor device of  claim 19 , wherein the metal silicide pattern comprises:
 a first metal silicide pattern disposed between the first source/drain region and the first metal contact; and   
     a second metal silicide pattern disposed between the second source/drain region and the second metal contact.