Method and system for global coverage analysis

Abstract

Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and non-implementation-specific design data. In an approach, both gate level and RTL level information are considered to perform coverage analysis.

1 . A method of performing automated coverage analysis, comprising:
 receiving a list of one or more constraint information for a circuit design; and   using both implementation-specific design data and non-implementation-specific design data about the circuit design to identify coverage for the circuit design.   
   
   
       2 . The method of  claim 1  in which the non-implementation-specific design data comprises architectural information. 
   
   
       3 . The method of  claim 2  in which the architectural information is selected from the group consisting of RTL code, VHDL code, Verilog code, behavioral code, synthesis pragmas, embedded assertions or constraints, side file assertions or constraints, macro cell information, library information, gate level design data, gate level design data augmented with information such as assertions, pragmas, side-files, constraints, macro cell information, and/or library information. 
   
   
       4 . The method of  claim 1  in which static timing analysis is employed to identify coverage. 
   
   
       5 . The method of  claim 1  in which gate-level, architectural information is used to perform the act of identifying coverage. 
   
   
       6 . The method of  claim 1  in which RTL-level architectural information is used to perform the act of identifying coverage. 
   
   
       7 . The method of  claim 6  comprising the act of mapping the constraint information onto RTL design data. 
   
   
       8 . The method of  claim 7  in which an equivalence checker is used to map onto the RTL design data. 
   
   
       9 . A system for performing coverage analysis, comprising a enhanced coverage analysis manager, the enhanced coverage analysis manager receiving design data and an initial list constraints, wherein the enhanced, coverage analysis manager is capable of identifying coverage based upon both implementation-specific and non-implementation-specific design data. 
   
   
       10 . The system of  claim 9  in which the design data comprises source code, Verilog code, VHDL code, gate level design data, RTL design data, assertion information, pragmas, side-files, constraints, macro cell information, library information, and/or architectural information. 
   
   
       11 . The system of  claim 9  in which the enhanced coverage analysis manager receives static timing analysis data. 
   
   
       12 . The system of  claim 11  in which the static timing analysis data includes the initial list of coverage and initial constraints. 
   
   
       13 . The system of  claims 9  in which the enhanced coverage analysis manager accesses one or more formal engines to identify the set of false paths 
   
   
       14 . The system of  claim 13  in which the one or more formal engines comprises an equivalence checker engine, a model checker engine, a logic sensitization engine or any engine using Boolean analysis techniques such as ATPG, Binary Decision Diagrams (BDDs) or Boolean Satisfiability (SAT) solvers. 
   
   
       15 . The system of  claim 9  in which the enhanced coverage analysis manager generates coverage constraints to provide information to provide complete coverage. 
   
   
       16 . The system of  claim 9  in which the enhanced coverage analysis manager generates global coverage information. 
   
   
       17 . A computer program product comprising a computer usable medium having executable code for executing a process for performing automated coverage analysis, the process comprising:
 receiving a list of one or more constraint information for a circuit design; and   using both implementation-specific design data and non-implementation-specific design data about the circuit design to identify coverage for the circuit design.   
   
   
       18 . The product of  claim 17  in which the non-implementation-specific design data comprises architectural information. 
   
   
       19 . The product of  claim 18  in which the architectural information is selected from the group consisting of RTL code, VHDL code, Verilog code, behavioral code, synthesis pragmas, embedded assertions or constraints, side file assertions or constraints, macro cell information, library information, gate level design data, gate level design data augmented with information such as assertions, pragmas, side-files, constraints, macro ceil information, and/or library information. 
   
   
       20 . The product of  claim 17  in which static timing analysis is employed to identify coverage. 
   
   
       21 . The product of  claim 17  in which gate-level architectural information is used to perform the act of identifying coverage. 
   
   
       22 . The product of  claim 17  in which RTL-level architectural information is used to perform the act of identifying coverage. 
   
   
       23 . The product of  claim 22  comprising the act of mapping the constraint information onto RTL design data. 
   
   
       24 . The product of  claim 23  in which an equivalence checker is used to map onto the RTL design data.