Inventor · disambiguated record
Manish Pandey
Also filed as: PANDEY MANISH · PANDEY MANISH JATASHANKER
25 granted patents·3 pending applications·224 citations·filing 2002–2022
96Inventor score
Top patents by PatentIndex Score
28 records- 0194US11605126B1Detecting fraud in credit applicationsWELLS FARGO BANK NA·Filed 2021·Granted Mar 14, 2023·4 cites·20 claims
- 0294US7739629B2Method and mechanism for implementing electronic designs having power information specifications backgroundCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 15, 2010·42 cites·29 claims
- 0392US7962886B1Method and system for generating design constraintsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jun 14, 2011·48 cites·26 claims
- 0489US8516422B1Method and mechanism for implementing electronic designs having power information specifications backgroundWANG QI·Filed 2010·Granted Aug 20, 2013·13 cites·31 claims
- 0584US11074302B1Anomaly visualization for computerized modelsWELLS FARGO BANK NA·Filed 2019·Granted Jul 27, 2021·4 cites·18 claims
- 0682US7694251B2Method and system for verifying power specifications of a low power designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Apr 6, 2010·16 cites·24 claims
- 0782US7669165B2Method and system for equivalence checking of a low power designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 23, 2010·16 cites·20 claims
- 0882US7587690B1Method and system for global coverage analysisCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Sep 8, 2009·11 cites·38 claims
- 0980USRE44479EMethod and mechanism for implementing electronic designs having power information specifications backgroundWANG QI·Filed 2012·Granted Sep 3, 2013·5 cites·29 claims
- 1079US10503853B1Formal verification using cached search path information to verify previously proved/disproved propertiesSYNOPSYS INC·Filed 2018·Granted Dec 10, 2019·3 cites·20 claims
- 1177US8627249B1Method and system for generating design constraintsPANDEY MANISH·Filed 2011·Granted Jan 7, 2014·9 cites·20 claims
- 1277US8209648B1Verifying multiple constraints for circuit designsKU SHAN-CHYUN·Filed 2009·Granted Jun 26, 2012·16 cites·21 claims
- 1374US11508009B1Trade asset cardWELLS FARGO BANK NA·Filed 2017·Granted Nov 22, 2022·1 cites·17 claims
- 1474US9430595B2Managing model checks of sequential designsSYNOPSYS INC·Filed 2012·Granted Aug 30, 2016·4 cites·27 claims
- 1570US11501048B1Estimating hardness of formal properties using on-the-fly machine learningSYNOPSYS INC·Filed 2018·Granted Nov 15, 2022·2 cites·20 claims
- 1667US11922505B1Trade asset cardWELLS FARGO BANK NA·Filed 2022·Granted Mar 5, 2024·0 cites·20 claims
- 1767US7266790B2Method and system for logic equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Sep 4, 2007·10 cites·44 claims
- 1865US6848084B1Method and apparatus for verification of memories at multiple abstraction levelsCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jan 25, 2005·12 cites·66 claims
- 1964US10140403B2Managing model checks of sequential designsSYNOPSYS INC·Filed 2016·Granted Nov 27, 2018·1 cites·15 claims
- 2063US7644380B1Method for analyzing circuits having MOS devicesCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jan 5, 2010·4 cites·38 claims
- 2162US8442111B2Optimal power usage in encoding data streamsGARG SHASHANK·Filed 2008·Granted May 14, 2013·3 cites·20 claims
- 2257US11599579B1Anomaly visualization for computerized modelsWELLS FARGO BANK NA·Filed 2021·Granted Mar 7, 2023·0 cites·17 claims
- 2352US2009064071A1Method and system for global coverage analysisCADENCE DESIGN SYSTEMS INC·Filed 2008·Application pending·0 cites
- 2448US7620919B2Method and system for logic equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 17, 2009·0 cites·17 claims
- 2548US7620918B2Method and system for logic equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 17, 2009·0 cites·25 claims
- 2647US2010250796A1Establishing a Secure Channel between a Server and a Portable DeviceJEVANS DAVID·Filed 2009·Application pending·0 cites
- 2743US10521536B2RTL verification using computational complexity-based property ranking and schedulingSYNOPSYS INC·Filed 2017·Granted Dec 31, 2019·0 cites·18 claims
- 2836US2022277394A1Process and system for deal structure optimizationWELLS FARGO BANK NA·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →