Cavity capacitor fabrication method and printed circuit board having embedded cavity capacitor

Abstract

A cavity capacitor fabrication method and a printed circuit board having an embedded cavity capacitor are disclosed. In accordance with an embodiment of the present invention, the printed circuit board having the embedded cavity capacitor includes two conductive layers to be used as a power layer and a ground layer, respectively; and a first dielectric layer, placed between the two conductive layers, wherein the cavity capacitor is placed between the two conductive layers, the cavity capacitor being formed to allow a second dielectric layer to have a lower stepped portion than the first dielectric layer, and the second dielectric layer using the two conductive layers as a first electrode and a second electrode, respectively, and placed between the first electrode and the second electrode.

1 . A printed circuit board having an embedded cavity capacitor, the printed circuit board, comprising:
 two conductive layers to be used as a power layer and a ground layer, respectively; and   a first dielectric layer, placed between the two conductive layers,   wherein the cavity capacitor is placed between the two conductive layers, the cavity capacitor being formed to allow a second dielectric layer to have a lower stepped portion than the first dielectric layer, and the second dielectric layer using the two conductive layers as a first electrode and a second electrode, respectively, and placed between the first electrode and the second electrode.   
     
     
         2 . The printed circuit board of  claim 1 , wherein the second dielectric layer is formed to have a higher dielectric constant than the first dielectric layer. 
     
     
         3 . The printed circuit board of  claim 1 , wherein a plurality of cavity capacitors are arranged between the two conductive layers. 
     
     
         4 . The printed circuit board of  claim 1 , wherein the cavity capacitor uses any one of the two conductive layers as any one electrode as it is. 
     
     
         5 . The printed circuit board of  claim 1 , wherein the cavity capacitor has any one shape of a circle, an ellipse and a polygon when viewed from an upper part of the printed circuit board. 
     
     
         6 . The printed circuit board of  claim 1 , wherein the cavity capacitor is formed close to any one of the two conductive layers,
 whereas a conductive material is charged to a cavity formed in a space between the other conductive layer and the cavity capacitor.   
     
     
         7 . The printed circuit board of  claim 6 , wherein the conductive material to be charged to the cavity is the same material as the other conductive layer or a conductive paste. 
     
     
         8 . A method of fabricating a cavity capacitor embedded in a printed circuit board including two conductive layers to be used as a power layer and a ground layer, respectively, and a first dielectric layer, placed between the two conductive layers, the method comprising:
 removing an upper conductive layer and the first dielectric layer excluding a lower conductive layer of the two conductive layers to allow a cavity to be formed between the two conductive layers, the lower conductive layer being supposed to be used as any one of electrodes of the cavity capacitor;   stacking a dielectric material on the cavity to allow a second dielectric layer having a lower stepped portion than the first dielectric layer to be formed in the cavity; and   stacking a conductive material on an upper part of the second dielectric layer and side parts of the cavity to allow the upper conductive layer to be used as the other electrode of the cavity capacitor.   
     
     
         9 . The method of  claim 8 , wherein the cavity capacitor has any one shape of a circle, an ellipse and a polygon when viewed from an upper part of the printed circuit board. 
     
     
         10 . The method of  claim 8 , wherein the second dielectric layer is formed to have a higher dielectric constant than the first dielectric layer. 
     
     
         11 . The method of  claim 8 , wherein, the step of stacking the conductive material on the upper part of the second dielectric layer and the side parts of the cavity comprises charging the conductive material to all spaces excluding a part in which the second dielectric layer is stacked in the cavity. 
     
     
         12 . The method of  claim 11 , wherein the conductive material is the same material as the first conductive layer or a conductive paste.