Registers for data transfers

Abstract

A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.

1 - 30 . (canceled) 
   
   
       31 . A processor comprising:
 multiple processing units; and   a register set configured and arranged to transfer information between at least two of the processing units;   where the register set comprises multiple registers configured to be selected in a first-in-first-out order by a ring operation performed with respect to the multiple registers in the first-in-first-out order.   
   
   
       32 . The processor of  claim 31 , further comprising:
 a Put register to indicate a destination register in the multiple registers; and   a Get register to indicate a source register in the multiple registers.   
   
   
       33 . The processor of  claim 31 , where the multiple processing units comprise programming engines arranged in a context pipeline configured to execute multiple threads, the register set comprises one of multiple register sets configured and arranged to transfer information between programming engines, and at least one of the multiple register sets comprises registers configured to be selected by a context-relative operation. 
   
   
       34 . The processor of  claim 33 , where the at least one of the multiple register sets comprises the register set comprising the multiple registers configured to be selected in the first-in-first-out order by the ring operation. 
   
   
       35 . The processor of  claim 34 , where the programming engines are configured to support a functional pipeline, and the multiple register sets are configured to support passing of a function in the functional pipeline between the programming engines. 
   
   
       36 . The processor of  claim 35 , where the functional pipeline relates to network packet processing tasks, and the multiple threads process network packets. 
   
   
       37 . The processor of  claim 35 , where the programming engines perform inter-thread signaling. 
   
   
       38 . The processor of  claim 34 , where each programming engine comprises a content addressable memory (CAM) to maintain context information for the programming engine. 
   
   
       39 . The processor of  claim 31 , where each of the multiple processing units comprises a control store to hold a microprogram for the processing unit to execute, and the processor further comprises a processor core to load the microprogram into the control store. 
   
   
       40 . A method comprising:
 performing operations using multiple processing units; and   transferring information between at least two of the processing units using a register set:   where the transferring comprises selecting registers of the register set in a first-in-first-out order by a ring operation performed with respect to the registers in the first-in-first-out order.   
   
   
       41 . The method of  claim 40 , where the transferring comprises:
 putting information into a destination register selected from the registers based on a value stored in a Put register; and   getting information from a source register selected from the registers based on a value stored in a Get register.   
   
   
       42 . A system comprising:
 a shared memory; and   a parallel, hardware-based multithreaded network processor comprising
 a memory controller, 
 multiple processing units, and 
 a register set configured and arranged to transfer information between at least two of the processing units, 
 where the register set comprises multiple registers configured to be selected in a first-in-first-out order by a ring operation performed with respect to the multiple registers in the first-in-first-out order. 
   
   
   
       43 . The system of  claim 42 , the processor further comprising:
 a Put register to indicate a destination register in the multiple registers; and   a Get register to indicate a source register in the multiple registers.   
   
   
       44 . The system of  claim 42 , where the multiple processing units comprise programming engines arranged in a context pipeline configured to execute multiple threads, the register set comprises one of multiple register sets configured and arranged to transfer information between programming engines, and at least one of the multiple register sets comprises registers configured to be selected by a context-relative operation. 
   
   
       45 . The system of  claim 44 , where the at least one of the multiple register sets comprises the register set comprising the multiple registers configured to be selected in the first-in-first-out order by the ring operation. 
   
   
       46 . The system of  claim 45 , where the programming engines are configured to support a functional pipeline, and the multiple register sets are configured to support passing of a function in the functional pipeline between the programming engines. 
   
   
       47 . The system of  claim 46 , where the functional pipeline relates to network packet processing tasks, and the multiple threads process network packets. 
   
   
       48 . The system of  claim 46 , where the programming engines perform inter-thread signaling. 
   
   
       49 . The system of  claim 45 , where each programming engine comprises a content addressable memory (CAM) to maintain context information for the programming engine. 
   
   
       50 . The system of  claim 42 , where each of the multiple processing units comprises a control store to hold a microprogram for the processing unit to execute, and the processor further comprises a processor core to load the microprogram into the control store.