Nonvolatile charge trap memory device having a high dielectric constant blocking region

Abstract

A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a high dielectric constant blocking region.

1 . A nonvolatile charge trap memory device, comprising:
 a substrate having a channel region, a source region and a drain region; and   a gate stack disposed above the substrate over the channel region and between the source region and the drain region, wherein the gate stack comprises a multi-layer blocking dielectric region.   
   
   
       2 . The nonvolatile charge trap memory device of  claim 1 , wherein the nonvolatile charge trap memory device is a SONOS-type device, the gate stack further comprising:
 a tunnel dielectric layer disposed above the channel region;   a charge-trapping layer disposed above the tunnel dielectric layer and below the multi-layer blocking dielectric region; and   a gate layer disposed above the multi-layer blocking dielectric region.   
   
   
       3 . The nonvolatile charge trap memory device of  claim 2 , wherein the multi-layer blocking dielectric region is a bi-layer blocking dielectric region having a first dielectric layer disposed directly above the charge-trapping layer and a second dielectric layer disposed directly above the first dielectric layer and directly below the gate layer, and wherein the dielectric constant of the first dielectric layer is lower than the dielectric constant of the second dielectric layer. 
   
   
       4 . The nonvolatile charge trap memory device of  claim 2 , wherein the multi-layer blocking dielectric region is a bi-layer blocking dielectric region having a first dielectric layer disposed directly above the charge-trapping layer and a second dielectric layer disposed directly above the first dielectric layer and directly below the gate layer, wherein the first dielectric layer has a large barrier height, and wherein the second dielectric layer has a high dielectric constant. 
   
   
       5 . The nonvolatile charge trap memory device of  claim 3 , wherein the first dielectric layer of the bi-layer blocking dielectric region comprises silicon dioxide, and wherein the second dielectric layer of the bi-layer blocking dielectric region comprises a material selected from the group consisting of silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide. 
   
   
       6 . The nonvolatile charge trap memory device of  claim 3 , wherein the first dielectric layer of the bi-layer blocking dielectric region comprises a material having a dielectric constant approximately in the range of 3.5-4.5, and wherein the second dielectric layer of the bi-layer blocking dielectric region comprises a material having a dielectric constant above approximately 7. 
   
   
       7 . The nonvolatile charge trap memory device of  claim 2 , wherein the tunnel dielectric layer comprises a high-K dielectric portion, wherein the charge-trapping layer comprises a bi-layer silicon oxy-nitride region, and wherein the gate layer is a high work-function gate layer. 
   
   
       8 . A nonvolatile charge trap memory device, comprising:
 a substrate having a channel region, a source region and a drain region; and   a gate stack disposed above the substrate over the channel region and between the source region and the drain region, wherein the gate stack comprises a graded blocking dielectric layer.   
   
   
       9 . The nonvolatile charge trap memory device of  claim 8 , wherein the nonvolatile charge trap memory device is a SONOS-type device, the gate stack further comprising;
 a tunnel dielectric layer disposed above the channel region;   a charge-trapping layer disposed above the tunnel dielectric layer and below the graded blocking dielectric layer; and   a gate layer disposed above the graded blocking dielectric layer.   
   
   
       10 . The nonvolatile charge trap memory device of  claim 9 , wherein the graded blocking dielectric layer is disposed directly above the charge-trapping layer and directly below the gate layer, and wherein the dielectric constant of the graded blocking dielectric layer has a low-to-high gradient in the direction from the charge-trapping layer to the gate layer. 
   
   
       11 . The nonvolatile charge trap memory device of  claim 10 , wherein the portion of the graded blocking dielectric layer directly adjacent to the charge-trapping layer consists essentially of silicon dioxide, and wherein the portion of the graded blocking dielectric layer directly adjacent to the gate layer consists essentially of silicon nitride. 
   
   
       12 . The nonvolatile charge trap memory device of  claim 10 , wherein the portion of the graded blocking dielectric layer directly adjacent to the charge-trapping layer consists essentially of silicon dioxide, and wherein the portion of the graded blocking dielectric layer directly adjacent to the gate layer consists essentially of a material selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide. 
   
   
       13 . The nonvolatile charge trap memory device of  claim 10 , wherein the portion of the graded blocking dielectric layer directly adjacent to the charge-trapping layer consists essentially of a material having a dielectric constant approximately in the range of 3.5-4.5, and wherein the portion of the graded blocking dielectric layer directly adjacent to the gate layer consists essentially of a material having a dielectric constant above approximately 7. 
   
   
       14 . The nonvolatile charge trap memory device of  claim 9 , wherein the tunnel dielectric layer comprises a high-K dielectric portion, wherein the charge-trapping layer comprises a bi-layer silicon oxy-nitride region, and wherein the gate layer is a high work-function gate layer. 
   
   
       15 . A method of fabricating a nonvolatile charge trap memory device, comprising:
 providing a substrate;   forming a gate stack above the substrate, wherein forming the gate stack comprises:
 forming a tunnel dielectric layer above the substrate; 
 forming a charge-trapping layer above the tunnel dielectric layer; 
 forming a blocking dielectric region above the charge-trapping layer, wherein the blocking dielectric region is formed from at least two different materials; 
 forming a gate layer above the blocking dielectric region; and 
 patterning the tunnel dielectric layer, the charge-trapping layer, the blocking dielectric region, and the gate layer; and 
   forming a source region and a drain region in the substrate and on other side of the gate stack to provide a channel region in the substrate and below the gate stack.   
   
   
       16 . The method of  claim 15 , wherein forming the blocking dielectric region from at least two different materials comprises oxidizing a top portion of the charge-trapping layer and, subsequently, depositing a dielectric layer above the oxidized portion of the charge-trapping layer. 
   
   
       17 . The method of  claim 15 , wherein forming the blocking dielectric region from at least two different materials comprises depositing a first dielectric layer having a first dielectric constant and, subsequently, depositing a second dielectric layer having a second dielectric constant. 
   
   
       18 . The method of  claim 17 , wherein the second dielectric constant is greater than the first dielectric constant. 
   
   
       19 . The method of  claim 15 , wherein the blocking dielectric region is a bi-layer blocking dielectric region having a first dielectric layer disposed directly above the charge-trapping layer and a second dielectric layer disposed directly above the first dielectric layer and directly below the gate layer, and wherein the dielectric constant of the first dielectric layer is lower than the dielectric constant of the second dielectric layer. 
   
   
       20 . The method of  claim 15 , wherein the blocking dielectric region is a graded blocking dielectric layer disposed directly above the charge-trapping layer and directly below the gate layer, and wherein the dielectric constant of the graded blocking dielectric layer has a low-to-high gradient in the direction from the charge-trapping layer to the gate layer.