Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement

Abstract

Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instabilty (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

1 . A dielectric layer stack in an integrated circuit comprised of 3 to 10 layers of dielectric material, comprised substantially of silicon nitride, wherein each layer is deposited in a deposition chamber and exposed to a nitrogen-containing plasma in the deposition chamber before deposition of a next layer. 
   
   
       2 . The dielectric layer stack of  claim 1 , wherein said layers of dielectric material, are formed by flowing SiH4 gas at 5 to 80 sccm, NH3 gas at 20 to 320 sccm and N2 gas at 2500 to 40,000 sccm into said deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of said deposition chamber at 300 C to 400 C, and forming a plasma in the SiH4 gas, NH3 gas, and N2 gas by supplying 10 to 150 watts RF power. 
   
   
       3 . The dielectric layer stack of  claim 2 , wherein said nitrogen-containing plasma is formed by flowing N2 gas at 2500 to 40,000 sccm into the deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of the deposition chamber at 300 C to 400 C, and forming a plasma in the N2 gas by supplying 10 to 200 watts RF power. 
   
   
       4 . The dielectric layer stack of  claim 2 , wherein a compressive stress is higher than 1300 MPa. 
   
   
       5 . The dielectric layer stack of  claim 2 , wherein chemical compositions of all said layers are not identical. 
   
   
       6 . The dielectric layer stack of  claim 5 , wherein a hydrogen content of a first layer is at least 25 atomic percent. 
   
   
       7 . The dielectric layer stack of  claim 6 , wherein a first layer is exposed for 10 to 150 seconds to a nitrogen-containing plasma formed of NH3, which is formed by flowing NH3 gas at 500 to 10,000 sccm into the deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of said deposition chamber at 300 C to 400 C, and supplying 10 to 200 watts RF power. 
   
   
       8 . An integrated circuit, comprising:
 provided a substrate;   a region of field oxide in said substrate;   an n-well in said substrate;   a p-well in said substrate;   an n-channel MOS transistor in said p-well comprising:
 a first gate dielectric on a top surface of said p-well; 
 a first gate structure on a top surface of said first gate dielectric; 
 n-type source and drain regions in said p-well adjacent to said first gate structure; and 
 a first set of silicide regions on, and in contact with, top surfaces of said n-type source and drain regions; 
   a p-channel MOS transistor in said n-well comprising:
 a second gate dielectric on a top surface of said n-well; 
 a second gate structure on a top surface of said second gate dielectric; 
 p-type source and drain regions in said n-well adjacent to said second gate structure; and 
 a second set of silicide regions on, and in contact with, top surfaces of said p-type source and drain regions; 
   a pre-metal dielectric liner layer stack on said n-channel transistor and said p-channel transistor, comprised of 3 to 10 layers of dielectric material, comprised substantially of silicon nitride, wherein each layer is deposited in a deposition chamber and exposed to a nitrogen-containing plasma in the deposition chamber before deposition of a next layer;   a pre-metal dielectric layer on said pre-metal dielectric liner layer stack; and   contacts in said pre-metal dielectric layer and said pre-metal dielectric liner layer stack, on, and electrically connected to, said n-type source and drain regions and said p-type source and drain regions.   
   
   
       9 . The integrated circuit of  claim 8 , wherein said layers of dielectric material, are formed by flowing SiH4 gas at 5 to 80 sccm, NH3 gas at 20 to 320 sccm and N2 gas at 2500 to 40,000 sccm into said deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of said deposition chamber at 300 C to 400 C, and forming a plasma in the SiH4 gas, NH3 gas, and N2 gas by supplying 10 to 150 watts RF power. 
   
   
       10 . The integrated circuit of  claim 9 , wherein said nitrogen-containing plasma is formed by flowing N2 gas at 2500 to 40,000 sccm into the deposition chamber to maintain a pressure of 1 to 100 torr, maintaining a temperature of the deposition chamber at 300 C to 400 C, and forming a plasma in the N2 gas by supplying 10 to 200 watts RF power. 
   
   
       11 . The integrated circuit of  claim 9 , wherein a compressive stress in said pre-metal dielectric liner layer stack is higher than 1300 MPa. 
   
   
       12 . The integrated circuit of  claim 9 , wherein chemical compositions of all said layers in said pre-metal dielectric liner layer stack are not identical. 
   
   
       13 . The integrated circuit of  claim 12 , wherein a hydrogen content of a first layer in said pre-metal dielectric liner layer stack is at least 25 atomic percent. 
   
   
       14 . The integrated circuit of  claim 13 , wherein a first layer is exposed for 10 to 150 seconds to a nitrogen-containing plasma formed of NH3, which is formed by flowing NH3 gas at 500 to 10,000 sccm into said deposition chamber while maintaining a pressure of 1 to 100 torr, maintaining a temperature of said deposition chamber at 300 C to 400 C, and supplying 10 to 200 watts RF power. 
   
   
       15 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate;   forming field oxide in said substrate;   forming an n-well in said substrate;   forming a p-well in said substrate;   forming an n-channel MOS transistor in said p-well by a process comprising the steps of:
 forming a first gate dielectric on a top surface of said p-well; 
 forming a first gate structure on a top surface of said first gate dielectric; 
 forming n-type source and drain regions in said p-well adjacent to said first gate structure; and 
 forming a first set of silicide regions on, and in contact with, top surfaces of said n-type source and drain regions; 
   forming a p-channel MOS transistor in said n-well by a process comprising the steps of:
 forming a second gate dielectric on a top surface of said n-well; 
 forming a second gate structure on a top surface of said second gate dielectric; 
 forming p-type source and drain regions in said n-well adjacent to said second gate structure; and 
 forming a second set of silicide regions on, and in contact with, top surfaces of said p-type source and drain regions; 
   forming a pre-metal dielectric liner layer stack on said n-channel transistor and said p-channel transistor, by a process comprised of the steps of:
 providing a deposition chamber; 
 inserting said substrate into said deposition chamber; 
 depositing a first silicon nitride layer on said n-channel transistor and said p-channel transistor by a process comprising the steps of:
 flowing SiH4 gas at 5 to 80 sccm into the deposition chamber; 
 flowing NH3 gas at 20 to 320 sccm into the deposition chamber; 
 flowing N2 gas at 2500 to 40,000 sccm into the deposition chamber; 
 maintaining a pressure of 1 to 100 torr in the deposition chamber; 
 maintaining a temperature of 300 C to 400 C in the deposition chamber; and 
 forming a plasma in the SiH4 gas, NH3 gas, and N2 gas by supplying 10 to 150 watts RF power; 
 
 exposing said first silicon nitride layer to a nitrogen-containing plasma in said deposition chamber; and 
 repeating said steps of depositing a silicon nitride layer and exposing the silicon nitride layer to a nitrogen-containing plasma for a plurality of iterations; 
   forming a pre-metal dielectric layer on said pre-metal dielectric liner layer stack; and   forming contacts in said pre-metal dielectric layer stack and in said pre-metal dielectric liner layer stack, on, and electrically connected to, said n-type source and drain regions and said p-type source and drain regions.   
   
   
       16 . The method of  claim 15 , wherein said nitrogen-containing plasma is formed by a process comprising the steps of:
 flowing N2 gas at 2500 to 40,000 sccm into the deposition chamber;   maintaining a pressure of 1 to 100 torr in the deposition chamber;   maintaining a temperature of 300 C to 400 C in the deposition chamber; and   forming a plasma in the N2 gas by supplying 10 to 200 watts RF power.   
   
   
       17 . The method of  claim 15 , wherein a compressive stress in said pre-metal dielectric liner layer stack is higher than 1300 MPa. 
   
   
       18 . The method of  claim 15 , wherein chemical compositions of all said layers in said pre-metal dielectric liner layer stack are not identical. 
   
   
       19 . The method of  claim 18 , wherein a hydrogen content of a first layer in said pre-metal dielectric liner layer stack is at least 25 atomic percent. 
   
   
       20 . The method of  claim 19 , wherein a first layer is exposed for 10 to 150 seconds to a nitrogen-containing plasma formed of NH3, which is formed by a process comprising the steps of:
 flowing NH3 gas at 500 to 10,000 sccm into said deposition chamber;   maintaining a pressure of 1 to 100 torr in said deposition chamber;   maintaining a temperature of 300 C to 400 C in said deposition chamber; and supplying 10 to 200 watts RF power.