Mos device structure

Abstract

The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

1 - 12 . (canceled) 
   
   
       13 . A semiconductor device structure, comprising:
 a substrate having at least an isolation structure to define an active region;   at least a gate structure disposed on the substrate in the active region, wherein a pair of spacers is disposed on both sidewalls of the gate structure, a pair of source/drain extension regions is disposed in the substrate and below the spacers, and a pair of trenches is disposed in the substrate at both sides of the gate structure;   a pair of source/drain region formed by a doped silicon germanium (SiGe) layer disposed in the trenches filling up the trenches, wherein an upper surface of the doped silicon germanium layer at least substantially levels with the substrate surface;   an amorphous silicon layer covering the upper surface of the doped silicon germanium layer in the trenches; and   a metal silicide layer disposed on the gate structure and on the amorphous silicon layer.   
   
   
       14 . The structure of  claim 13 , wherein the amorphous silicon layer has a thickness of about 20 angstroms to about 300 angstroms. 
   
   
       15 . The structure of  claim 13 , wherein the source/drain region further comprises an undoped silicon germanium layer disposed between the trench and the doped silicon germanium layer. 
   
   
       16 . The structure of  claim 13 , wherein a material of the metal silicide layer is selected from the group consisting of nickel silicide, nickel platinum silicide, a combination of both and an alloy of both. 
   
   
       17 . The structure of  claim 13 , wherein the spacer is a double spacer structure. 
   
   
       18 . The structure of  claim 13 , wherein the doped silicon germanium layer is a boron doped silicon germanium layer formed by in-situ boron doping selective SiGe epitaxy growth process. 
   
   
       19 . The structure of  claim 13 , wherein the amorphous silicon layer is a amorphous silicon epitaxy layer formed by selective silicon epitaxy growth process. 
   
   
       20 . The structure of  claim 13 , wherein the upper surface of the doped silicon germanium layer is higher than the substrate surface.