Semiconductor package and method of attaching semiconductor dies to substrates

Abstract

A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.

1 . A method of mounting a semiconductor die on a substrate with a solder mask on a first surface comprising:
 placing a die on said solder mask;   mounting said die to said substrate by applying pressure and heat.   
   
   
       2 . The method of  claim 1  wherein said applied pressure ranges from a bond force of approximately 5 to 10 Kg. 
   
   
       3 . The method of any one of  claims 1  and  2  wherein said heat has a temperature range from approximately 150 to 200° C. 
   
   
       4 . The method of any one of  claims 1  and  2  wherein said pressure is applied for a range of approximately 1 to 10 seconds. 
   
   
       5 . The method of  claim 1  wherein said heat causes said solder mask to adhere said die to said substrate. 
   
   
       6 . The method of  claim 1  wherein said applied pressure is a bond force of approximately 5 Kg. 
   
   
       7 . The method of any one of  claims 1  and  6  wherein said heat has a temperature of approximately 175° C. 
   
   
       8 . The method of any one of  claims 1  and  6  wherein said pressure is applied for approximately 5 seconds. 
   
   
       9 . The method of  claim 1  wherein said solder mask is not pre-baked before said die is attached. 
   
   
       10 . A semiconductor package comprising:
 a semiconductor die;   a substrate; and   a solder mask;   wherein said solder mask adheres said die to said substrate.   
   
   
       11 . The semiconductor package of  claim 10 , wherein said substrate further comprises a core and a metal layer wherein said metal layer is between said core and said solder mask. 
   
   
       12 . The semiconductor package of  claim 10 , wherein said solder mask comprises acrylic epoxy. 
   
   
       13 . The semiconductor package of  claim 10 , wherein said solder mask has a thickness of approximately at least 30 μm.