Method of forming a recess channel trench pattern, and fabricating a recess channel transistor

Abstract

A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.

1 . A recess channel transistor comprising:
 source and drain regions formed in an active region of a semiconductor substrate defined by a device isolating layer; and   a recess gate formed by filling a recess channel trench in the semiconductor substrate,   wherein a width of the recess channel trench in a gate line direction at the level of the surface of the semiconductor substrate is larger than a width of the recess channel trench defined by the device isolating layer in the gate line direction at the depth of the bottom of the recess gate, and the bottom surface of the recess gate defined by the isolating layer is substantially flat.   
   
   
       2 . The recess channel transistor of  claim 1 , wherein the recess gate comprising:
 a gate insulating layer formed along the recess channel trench;   a gate conductive layer formed by filling the recess channel trench; and   a capping layer.   
   
   
       3 . The recess channel transistor of  claim 2 , wherein the gate conductive layer is comprised of a polysilicon layer and a gate metal layer sequentially stacked.