Circuitry and gate stacks

Abstract

The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.

1 . A gate structure, comprising:
 a gate oxide layer disposed on a semiconductor substrate;   a polysilicon layer disposed on the gate oxide layer;   a metal silicide layer disposed on the polysilicon layer;   a Si x N y O z :H layer disposed on the metal silicide layer, wherein the metal silicide layer is subjected to an anneal treatment after the Si x N y O z :H layer is disposed to protect the metal silicide layer during the anneal; and   a silicon nitride layer disposed on the Si x N y O z :H layer, wherein the polysilicon layer, the gate oxide layer, the metal silicide layer, the Si x N y O z :H layer and the silicon nitride layer are patterned to form the gate structure, wherein the final thicknesses of both the silicon nitride layer and the Si x N y O z :H layer are optimized to cooperatively minimize reflection back into an overlying layer of photoresist.   
   
   
       2 . The gate structure of  claim 1 , wherein the relative values of x, y and z are selected to alter an absorbance characteristic. 
   
   
       3 . The gate structure of  claim 2 , wherein x ranges between approximately 0.39 and 0.65, y ranges between approximately 0.02 to 0.56 and z ranges between approximately 0.05 to 0.33. 
   
   
       4 . The gate structure of  claim 1 , wherein the metal in the silicide layer comprises one of titanium and tungsten. 
   
   
       5 . The gate structure of  claim 1 , wherein the Si x N y O z :H layer ranges in thickness between approximately 300 Å and approximately 650 Å. 
   
   
       6 . A gate structure, comprising:
 a gate oxide layer formed on a supporting substrate;   a polysilicon layer formed on the gate oxide layer;   a metal silicide layer formed on the polysilicon layer;   an antireflective layer formed on the metal silicide layer, wherein the metal silicide layer is annealed after the antireflective layer is disposed on the metal silicide layer; and   a silicon nitride layer formed on the antireflective layer, wherein the polysilicon layer, the gate oxide layer, the metal silicide layer, the antireflective layer and the silicon nitride layer are patterned to define a gate stack, further wherein the selected thicknesses of at least one of the silicon nitride layer and the antireflective layer cooperatively minimize reflection back into an overlying layer of photoresist.   
   
   
       7 . The gate structure of  claim 6 , wherein the antireflective layer comprises silicon, nitrogen, oxygen and hydrogen in a predetermined composition. 
   
   
       8 . The gate structure of  claim 7 , wherein the predetermined composition comprises Si x N y O z :H, wherein x ranges between approximately 0.39 and 0.65, y ranges between approximately 0.02 to 0.56 and z ranges between approximately 0.05 to 0.33. 
   
   
       9 . The gate structure of  claim 6 , wherein the metal silicide layer comprises one of a titanium silicide and a tungsten silicide. 
   
   
       10 . A gate structure, comprising:
 a metal silicide layer;   an antireflective layer abutting the metal silicide layer that is subjected to an anneal treatment to protect the metal silicide layer during the anneal; and   a silicon nitride layer abutting the antireflective layer wherein the metal silicide layer, the antireflective layer and the silicon nitride layer are patterned to form the gate structure, wherein the selected thicknesses of the silicon nitride layer and the antireflective layer cooperatively minimize reflection back into a layer of photoresist.   
   
   
       11 . The gate structure of  claim 10 , comprising a supporting substrate that includes a gate oxide layer disposed on the substrate, and a polysilicon layer disposed on the gate oxide layer, wherein the polysilicon layer abuts the metal silicide layer. 
   
   
       12 . The gate structure of  claim 10 , wherein the antireflective layer comprises Si x N y O z :H, wherein x ranges between approximately 0.39 and 0.65, y ranges between approximately 0.02 to 0.56 and z ranges between approximately 0.05 to 0.33. 
   
   
       13 . The gate structure of  claim 10 , wherein the metal silicide layer comprises one of a titanium silicide and a tungsten silicide. 
   
   
       14 . The gate structure of  claim 11 , wherein the gate oxide layer and the polysilicon layer are patterned with the metal silicide layer, the antireflective layer and the silicon nitride layer. 
   
   
       15 . A gate structure, comprising:
 a gate oxide layer disposed on a semiconductor substrate;   a polysilicon layer disposed on the gate oxide layer;   an annealed, metal silicide layer disposed on the polysilicon layer;   a Si x N y O z :H layer disposed on the metal silicide layer during the anneal and configured to act as an antireflective layer; and   a silicon nitride layer disposed on the Si x N y O z :H layer and wherein the thicknesses of the silicon nitride layer and the Si x N y O z :H layer are optimized in combination to cooperatively minimize reflection back into a layer of photoresist.   
   
   
       16 . The gate structure of  claim 15 , wherein the silicon nitride layer has a thickness greater than 1000 Å. 
   
   
       17 . The gate structure of  claim 15 , wherein the relative values of x, y and z are selected to alter an absorbance characteristic. 
   
   
       18 . The gate structure of  claim 17 , wherein x ranges between approximately 0.39 and 0.65, y ranges between approximately 0.02 to 0.56 and z ranges between approximately 0.05 to 0.33. 
   
   
       19 . The gate structure of  claim 15 , wherein the metal silicide layer comprises one of a titanium silicide and a tungsten silicide. 
   
   
       20 . The gate structure of  claim 15 , wherein the Si x N y O z :H layer ranges in thickness between approximately 300 Å and approximately 650 Å.