Cmos transistor and the method for manufacturing the same

Abstract

A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

1 . A method of forming a CMOS transistor, comprising:
 providing a semiconductor substrate having at least an NMOS transistor and at least a PMOS transistor thereon, and a source/drain of the PMOS transistor comprising germanium (Ge);   forming a carbon-doped layer in the top portion of the source/drain of the PMOS transistor;   performing a self-aligned silicide process;   forming at least a tensile thin film covering the semiconductor substrate, the NMOS transistor, and the PMOS transistor; and   performing a surface treatment on the tensile thin film.   
   
   
       2 . The method of  claim 1 , wherein the carbon-doped layer is formed by a carbon implantation process. 
   
   
       3 . The method of  claim 2 , wherein the carbon implantation process is performed with an implantation energy between 1 KeV and 5 KeV, and with an implantation dosage between 10 13  atom/cm 2  and 10 16  atom/cm 2 . 
   
   
       4 . The method of  claim 2 , wherein the source/drain of the PMOS transistor is formed comprising a step of a heavy doped implantation process to implant P-type dopant into the semiconductor substrate, and the carbon implantation process is performed before the heavy doped implantation process. 
   
   
       5 . The method of  claim 2 , wherein the source/drain of the PMOS transistor is formed comprising a step of a heavy doped implantation process to implant P-type dopant into the semiconductor substrate, and the carbon implantation process is performed after the heavy doped implantation process. 
   
   
       6 . The method of  claim 1 , wherein the source/drain of the PMOS transistor is formed comprising steps of:
 performing a etch process to form at least a recess on the surface of the semiconductor substrate in the PMOS transistor; and   performing a selective epitaxial growth process to form a SiGe epitaxial layer in the recess, wherein the carbon-doped layer is formed during the selective epitaxial growth process.   
   
   
       7 . The method of  claim 6 , wherein the selective growth process comprises carbon as material. 
   
   
       8 . The method of  claim 7 , wherein the concentration of the carbon is increased during the formation of the SiGe epitaxial layer. 
   
   
       9 . The method of  claim 1 , wherein the surface treatment comprises a rapid thermal process (RTP) or an UV curing process. 
   
   
       10 . The method of  claim 1 , wherein the tensile thin film comprises a multi-layered tensile thin film. 
   
   
       11 . The method of  claim 10 , wherein the multi-layered tensile thin film comprises a buffered tensile thin film and a high tensile thin film, and the buffered tensile thin film has a lower tensile stress than that of the high tensile thin film. 
   
   
       12 . The method of  claim 1 , further comprising forming a high compressive thin film covering the PMOS transistor after the tensile thin film is formed. 
   
   
       13 . A CMOS transistor, comprising:
 a semiconductor substrate;   at least an NMOS transistor disposed on the semiconductor substrate, the NMOS transistor comprising a P well , a gate structure disposed on a surface of the P well, and a source/drain beside the gate structure;   at least a PMOS transistor disposed on the semiconductor substrate, the PMOS transistor comprising an N well, a gate structure disposed on a surface of the N well, and a source/drain beside the gate structure, wherein the source/drain of the PMOS transistor comprises a carbon-doped layer in the top portion thereof; and   a contact hole etch stop layer (CESL) disposed on the NMOS transistor and the PMOS transistor.   
   
   
       14 . The CMOS transistor of  claim 13 , wherein the source/drain of the PMOS transistor comprises Ge. 
   
   
       15 . The CMOS transistor of  claim 14 , wherein the source/drain of the PMOS transistor comprises a SiGe epitaxial layer. 
   
   
       16 . The CMOS transistor of  claim 13 , wherein the carbon-doped layer has a thickness between 100 angstrom (Å) and 500 Å. 
   
   
       17 . The CMOS transistor of  claim 13 , wherein a salicide layer is disposed on each of the source/drain, and the silicide layer has a thickness between 50 Å and 500 Å. 
   
   
       18 . The CMOS transistor of  claim 10 , wherein a portion of the CESL disposed on the NMOS comprises a tensile thin film, and the other portion of the CESL disposed on the PMOS comprises a high compressive thin film. 
   
   
       19 . The CMOS transistor of  claim 18 , wherein the tensile thin film comprises a multi-layered tensile thin film. 
   
   
       20 . The CMOS transistor of  claim 19 , wherein the multi-layered tensile thin film comprises a buffered tensile thin film and a high tensile thin film, and the buffered tensile thin film has a lower tensile stress than that of the high tensile thin film.