Inventor · disambiguated record
Jei-Ming Chen
Also filed as: CHEN JEI-MING
36 granted patents·30 pending applications·209 citations·filing 2003–2025
97Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD21UNITED MICROELECTRONICS CORP21CHEN JEI-MING8CHEN MEI-LING3CHEN NENG-KUO2
Top patents by PatentIndex Score
66 records- 0198US11887851B2Method for forming and using maskTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jan 30, 2024·4 cites·20 claims
- 0296US11482411B2Semiconductor device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Oct 25, 2022·3 cites·20 claims
- 0395US8709901B1Method of forming an isolation structureUNITED MICROELECTRONICS CORP·Filed 2013·Granted Apr 29, 2014·26 cites·16 claims
- 0494US11842922B2Method for forming interconnect structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Dec 12, 2023·2 cites·20 claims
- 0593US10332746B1Post UV cure for gapfill improvementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 25, 2019·9 cites·20 claims
- 0691US8772904B2Semiconductor structure and process thereofLIU CHIH-CHIEN·Filed 2012·Granted Jul 8, 2014·12 cites·6 claims
- 0790US8580625B2Metal oxide semiconductor transistor and method of manufacturing the sameLU TSUO-WEN·Filed 2011·Granted Nov 12, 2013·13 cites·26 claims
- 0889US7378343B2Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon contentUNITED MICROELECTRONICS CORP·Filed 2005·Granted May 27, 2008·20 cites·20 claims
- 0988US10777466B2Semiconductor Fin cutting process and structures formed therebyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Sep 15, 2020·4 cites·20 claims
- 1088US9362358B2Spatial semiconductor structureUNITED MICROELECTRONICS CORP·Filed 2015·Granted Jun 7, 2016·6 cites·5 claims
- 1188US8951884B1Method for forming a FinFET structureUNITED MICROELECTRONICS CORP·Filed 2013·Granted Feb 10, 2015·7 cites·11 claims
- 1288US8536038B2Manufacturing method for metal gate using ion implantationWang shao-wei·Filed 2011·Granted Sep 17, 2013·10 cites·35 claims
- 1387US8937369B2Transistor with non-uniform stress layer with stress concentrated regionsUNITED MICROELECTRONICS CORP·Filed 2012·Granted Jan 20, 2015·7 cites·21 claims
- 1487US8674452B2Semiconductor device with lower metal layer thickness in PMOS regionCHIEN CHIN-CHENG·Filed 2011·Granted Mar 18, 2014·10 cites·5 claims
- 1585US12341011B2Method for forming and using maskTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jun 24, 2025·0 cites·20 claims
- 1682US12322590B2Semiconductor device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 3, 2025·0 cites·20 claims
- 1782US9502305B2Method for manufacturing CMOS transistorUNITED MICROELECTRONICS CORP·Filed 2013·Granted Nov 22, 2016·4 cites·9 claims
- 1882US6873057B2Damascene interconnect with bi-layer capping filmUNITED MICROELECTRTONICS CORP·Filed 2003·Granted Mar 29, 2005·38 cites·4 claims
- 1982US2025285866A1Method for forming and using maskTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2081US12308283B2Method for forming interconnect structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted May 20, 2025·0 cites·20 claims
- 2181US10957585B2Semiconductor device and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Mar 23, 2021·5 cites·20 claims
- 2281US2024282638A1Semiconductor Fin Cutting Process and Structures Formed TherebyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2380US2025266292A1Method for forming interconnect structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2479US11854798B2Semiconductor device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 26, 2023·0 cites·20 claims
- 2579US8927388B2Method of fabricating dielectric layer and shallow trench isolationUNITED MICROELECTRONICS CORP·Filed 2012·Granted Jan 6, 2015·4 cites·19 claims
- 2678US11990375B2Semiconductor Fin cutting process and structures formed therebyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted May 21, 2024·0 cites·20 claims
- 2777US8692332B2Strained-silicon transistor and method of making the sameCHEN JEI-MING·Filed 2010·Granted Apr 8, 2014·9 cites·7 claims
- 2876US2024387189A1Method for forming semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2975US10727064B2Post UV cure for gapfill improvementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jul 28, 2020·1 cites·20 claims
- 3075US2024363452A1Methods of determining process recipes and forming a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 3173US7439154B2Method of fabricating interconnect structureUNITED MICROELECTRONICS CORP·Filed 2006·Granted Oct 21, 2008·6 cites·9 claims
- 3271US12087644B2Methods of determining process recipes and forming a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 10, 2024·0 cites·20 claims
- 3371US11380593B2Semiconductor fin cutting process and structures formed therebyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 5, 2022·0 cites·20 claims
- 3468US12217971B2Method for forming semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 4, 2025·0 cites·20 claims
- 3568US9034759B2Method for forming interlevel dielectric (ILD) layerUNITED MICROELECTRONICS CORP·Filed 2013·Granted May 19, 2015·2 cites·19 claims
- 3664US9034726B2Semiconductor processUNITED MICROELECTRONICS CORP·Filed 2014·Granted May 19, 2015·1 cites·11 claims
- 3760US7514347B2Interconnect structure and fabricating method thereofUNITED MICROELECTRONICS CORP·Filed 2006·Granted Apr 7, 2009·2 cites·16 claims
- 3856US2009280614A1Method of making a P-type metal-oxide semiconductor transistor and method of making a complementary metal-oxide semiconductor transistorCHEN NENG-KUO·Filed 2009·Application pending·0 cites
- 3955US9343573B2Method of fabrication transistor with non-uniform stress layer with stress concentrated regionsUNITED MICROELECTRONICS CORP·Filed 2014·Granted May 17, 2016·0 cites·12 claims
- 4055US2015132966A1Method for forming a finfet structureUNITED MICROELECTRONICS CORP·Filed 2014·Application pending·0 cites
- 4153US2010001317A1Cmos transistor and the method for manufacturing the sameCHEN YI-WEI·Filed 2008·Application pending·0 cites
- 4252US9105582B2Spatial semiconductor structure and method of fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2013·Granted Aug 11, 2015·0 cites·8 claims
- 4352US2008293194A1Method of making a P-type metal-oxide semiconductor transistor and method of making a complementary metal-oxide semiconductor transistorCHEN NENG-KUO·Filed 2007·Application pending·0 cites
- 4451US6960522B2Method for making damascene interconnect with bilayer capping filmUNITED MICROELECTRONICS CORP·Filed 2004·Granted Nov 1, 2005·4 cites·5 claims
- 4551US2009275211A1Fabrication method of porous low-k dielectric filmCHEN MEI-LING·Filed 2009·Application pending·0 cites
- 4650US2008237662A1Semiconductor device and method of fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2008·Application pending·0 cites
- 4749US2009146311A1Interconnect structureUNITED MICROELECTRONICS CORP·Filed 2009·Application pending·0 cites
- 4849US2014035070A1Metal oxide semiconductor transistorUNITED MICROELECTRONICS CORP·Filed 2013·Application pending·0 cites
- 4948US2008237658A1Semiconductor device and method of fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2007·Application pending·0 cites
- 5044US2015206803A1Method of forming inter-level dielectric layerUNITED MICROELECTRONICS CORP·Filed 2014·Application pending·0 cites
Showing the top 50 of 66 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Jei-Ming Chen files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →