Method of manufacturing semiconductor integrated circuit device having capacitor element

Abstract

In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

1 . A semiconductor integrated circuit device comprising:
 a semiconductor substrate including a first n-channel MISFET, formed in a first region of the substrate, and a memory cell formed in a memory cell forming region of the substrate,   the first n-channel MISFET having a gate electrode formed over the first region and a source region and a drain region formed in the substrate,   the memory cell including a selecting MISFET and a capacitor element electrically coupled to the selecting MISFET,   the selecting MISFET having a gate electrode formed over a circuit element forming region and semiconductor regions formed in the substrate, the semiconductor regions serving as a source region and a drain region of the selecting MISFET;   a first insulating film including silicon and nitrogen and formed so as to cover the gate electrodes and the drain regions of the first n-channel MISFET and the selecting MISFET;   a second insulating film formed on the first insulating film so as to cover the first insulating film such that after planarizing a surface of the first insulating film, the second insulating film is etched by using the first insulating film as an etching stopper to form a first opening and a second opening and such that the first insulating film within the first and second openings is etched so as to expose the drain region of the first n-channel MISFET in the first opening and to expose the semiconductor regions of the selecting MISFET in the second opening;   a first conductive film formed in the first opening so as to electrically connect to the drain region of the first n-channel MISFET; and   a second conductive film formed in the second opening so as to electrically connect to the semiconductor regions of the selecting MISFET.   
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein the first insulating film is comprised of a silicon nitride film. 
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , wherein the memory cell is a memory cell of a dynamic random access memory. 
     
     
         4 . The semiconductor integrated circuit device according to  claim 1 , wherein the capacitor element is formed over the substrate. 
     
     
         5 . The semiconductor integrated circuit device according to  claim 1 , wherein the first conductive film and the second conductive film are filled in the first opening and the second opening, respectively, and
 wherein the first conductive film and the second conductive film are comprised of metal material.   
     
     
         6 . The semiconductor integrated circuit device according to  claim 1 , wherein the first conductive film and the second conductive film are comprised of metal material. 
     
     
         7 . The semiconductor integrated circuit device according to  claim 1 , wherein the first n-channel MISFET constitutes a memory cell of a static random access memory. 
     
     
         8 . A semiconductor integrated circuit device comprising:
 a semiconductor substrate including a first n-channel MISFET, formed in a first region of the substrate, and a memory cell formed in memory cell forming region of the substrate,   the first n-channel MISFET having a gate electrode formed over the first region and a source region and a drain region formed in the substrate,   the memory cell including a selecting MISFET and a capacitor element electrically coupled to the selecting MISFET,   the selecting MISFET having a gate electrode formed over the circuit element forming region and semiconductor regions formed in the substrate, the semiconductor regions serving as a source region and a drain region of the selecting MISFET;   a first insulating film including silicon and nitrogen and formed so as to cover the gate electrodes and the drain regions of the first n-channel MISFET and the selecting MISFET;   a second insulating film formed on the first insulating film so as to cover the first insulating film such that after planarizing a surface of the first insulating film, the second insulating film is etched by using the first insulating film as an etching stopper to form a first opening and a second opening and such that the first insulating film within the first and second openings is etched so as to expose the drain region of the first n-channel MISFET in the first opening and to expose the semiconductor regions of the selecting MISFET in the second opening;   a first conductive film formed in the first opening so as to electrically connect to the drain region of the first n-channel MISFET;   a second conductive film formed in the second opening so as to electrically connect to the semiconductor regions of the selecting MISFET;   a third insulating film formed over the second insulating film and the capacitor element, the third insulating film having a third opening and a fourth opening;   a wiring line formed over the third insulating film and electrically connected to the first conductive film through the third opening; and   a data line formed over the third insulating film and electrically connected to the second conductive film through the fourth opening.   
     
     
         9 . The semiconductor integrated circuit device according to  claim 8 , wherein the first insulating film is comprised of a silicon nitride film. 
     
     
         10 . The semiconductor integrated circuit device according to  claim 8 , wherein the memory cell is a memory cell of a dynamic random access memory. 
     
     
         11 . The semiconductor integrated circuit device according to  claim 8 , wherein the capacitor element is formed over the substrate. 
     
     
         12 . The semiconductor integrated circuit device according to  claim 8 , wherein the first conductive film and the second conductive film are filled in the first opening and the second opening, respectively, and
 wherein the first conductive film and the second conductive film are comprised of metal material.   
     
     
         13 . The semiconductor integrated circuit device according to  claim 8 , wherein the first conductive film and the second conductive film are comprised of metal material. 
     
     
         14 . The semiconductor integrated circuit device according to  claim 8 , wherein the first n-channel MISFET constitutes a memory cell of a static random access memory.