Contact Structures in Substrate Having Bonded Interface, Semiconductor Device Including the Same, Methods of Fabricating the Same

Abstract

On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.

1 . A contact structure comprising:
 a first insulation layer on at least a portion of a first substrate;   a second substrate coupled to the first insulation layer;   a recess in the second substrate to have a portion thereof below an interface between the second substrate and the first insulation layer;   a second layer to cover the interface in the recess; and   a conductor to contact the lower insulation layer via the recess.   
     
     
         2 . The contact structure of  claim 1 , where the interface between the second substrate and the first insulation layer is a physical bonded interface, the conductor to cross a bottom surface of the recess. 
     
     
         3 . The contact structure of  claim 1 , where the recess is a groove, where an exposed interface is in a sidewall of the groove, where the conductor is a contact plug spaced apart from the exposed interface. 
     
     
         4 . The contact structure of  claim 1 , where the second substrate comprises a first semiconductor layer or a second semiconductor layer and a buffer layer; and
 where the first insulation layer is to bond to the first semiconductor layer or the buffer layer, the conductor to electrically connect to the first substrate without exposing the covered interface.   
     
     
         5 . The contact structure of  claim 4 , where the buffer layer comprises an insulating buffer layer, the conductor to directly contact the first substrate. 
     
     
         6 . The contact structure of  claim 1 , comprising a contact pad between the conductor and the lower substrate, where the conductor is electrically connected to the lower substrate through the contact pad. 
     
     
         7 . The contact structure of  claim 1 , comprising a gate electrode between the conductor and the first substrate, where the conductor is electrically connected to the gate electrode, where the second layer is subsequently removed. 
     
     
         8 . The contact structure of  claim 1 , where the second layer is a second insulation layer to fill the recess, the conductor to contact only the second layer in the recess in the second substrate, comprising a wiring on the second insulation layer, the wiring being configured to electrically connect to the conductor. 
     
     
         9 . The contact structure of  claim 1 , comprising:
 a multi-level flash memory device; and   a controller to control the flash memory device.   
     
     
         10 . A method of fabricating a semiconductor device, the method comprising:
 forming a lower insulation layer on a lower substrate;   disposing an upper substrate at the lower insulation layer;   forming a groove penetrating the upper substrate and into the lower insulation layer, the groove having a bottom surface that is lower than an interface between the upper substrate and the lower insulation layer;   forming a contact device in at least a portion of the groove extending over the lower insulation layer; and   forming an upper insulation layer to cover the interface exposed in the groove.   
     
     
         11 . The method of  claim 10 , where the disposing of the upper substrate on the lower insulation layer comprises:
 providing the upper substrate; and   physically bonding the upper substrate onto the lower insulation layer.   
     
     
         12 . The method of  claim 10 , where the groove is formed to have a sidewall comprising the exposed interface;
 where the upper insulation layer is to cover the bottom surface of the groove; and   where the contact device is to penetrate the upper insulation layer physically spaced apart from the interface.   
     
     
         13 . The method of  claim 10 , where:
 the upper substrate comprises a semiconductor layer or an insulating buffer layer and the semiconductor layer; and   the lower insulation layer covers the entire lower substrate and is bonded onto the semiconductor layer or the insulating buffer layer, respectively.   
     
     
         14 . The method of  claim 10 , where forming the contact device comprises forming a contact plug to electrically contact the lower substrate by direct physical contact with the lower substrate or by forming a first intermediate component to provide the electrical contact with the lower substrate, where the first intermediate component comprises a gate electrode or a contact pad between the lower substrate and the contact plug. 
     
     
         15 . The method of  claim 10 , comprising:
 forming a lower memory cell unit at the lower substrate;   forming an upper memory cell unit at the upper substrate;   where the upper insulation layer is on the upper substrate and the upper memory cell unit to fill a bit line groove,   and where the lower memory cell unit and the upper memory cell unit are a lower NAND flash memory cell unit and an upper NAND flash memory cell unit including an upper NAND string, respectively.   
     
     
         16 . The method of  claim 15 , comprising:
 forming a first node groove and a second node groove, the first node groove penetrating the upper substrate between a bit line contact plug and the upper NAND string to extend into the lower insulation layer, the second node groove penetrating the upper substrate adjacent to the upper NAND string and opposite to the first node groove to extend into the lower insulation layer, the first and second node grooves each having bottom surfaces lower than the interface;   forming a first node plug and second node plug, the first node plug penetrating the upper insulation layer in the first node groove to extend into the lower insulation layer and to be electrically connected to the lower substrate adjacent to a selection transistor and opposite to the bit line contact plug, the second node plug penetrating the upper insulation layer in the second node groove to extend into the lower insulation layer and to be electrically connected to the lower substrate between the ground selection transistor and the lower cell unit transistors; and   forming a first connector and a second connector, the first connector penetrating the upper insulation layer to electrically connect the upper substrate between the first node plug and the upper NAND string with the first node plug, the second connector penetrating the upper insulation layer to electrically connect the upper substrate between the second node plug and the upper NAND sting with the second node plug, where the first and second node grooves and the bit line groove are simultaneously formed.   
     
     
         17 . A memory system, comprising:
 a multi-level memory device; and   a controller to control the memory device, the memory device comprising:
 a lower substrate comprising a lower memory cell unit; 
 a lower insulation layer over portions of the lower memory cell unit; 
 an upper substrate to bond to the lower insulation layer, the upper substrate comprising an upper memory cell unit; 
 a groove to extend from the upper substrate into the lower insulation layer below an interface between the upper substrate and the lower insulation layer; and 
 a first contact plug in the groove spaced apart from the interface in the groove to contact the lower insulation layer, the first contact plug being electrically connected to the lower substrate, the first contact plug separated from the interface. 
   
     
     
         18 . The semiconductor device of  claim 17 , where the multi-level memory device comprises a plurality of layers stacked vertically, each of the plurality of layers including a plurality of memory cells, where memory cells in at least two layers of the plurality of layers belong to a single memory block, where first conductive lines select individual cells in a memory block, and where second conductive lines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled. 
     
     
         19 . The semiconductor device of  claim 17 , comprising an upper insulation layer to cover the interface exposed in the groove, the first contact plug physically separated from the interface by at least the upper insulation layer, where the lower memory cell unit comprises a
 lower flash memory cell unit that includes a lower NAND string having a string selection transistor, a plurality of lower cell transistors, and a ground selection transistor that are coupled in series and   the upper flash memory cell unit comprises an upper NAND string that includes a plurality of upper cell transistors that are coupled in series.   
     
     
         20 . The semiconductor device of  claim 19 , further comprising:
 a first node groove to penetrate the upper substrate between a bit line contact plug and the upper NAND stings to extend into the lower insulation layer, the first node groove having a bottom surface lower than the interface;   a first node plug to penetrate the upper insulation layer in the first node groove to extend into the lower insulation layer, the first node plug electrically connected to the lower substrate adjacent to the string selection transistor and opposite to a bit line plug;   a first connector to penetrate the upper insulation layer to connect the upper substrate between the first node plug and the upper NAND string with the first node plug electrically;   a second node groove to penetrate the upper substrate adjacent to the upper NAND string and opposite to the first node plug to extend into the lower insulation layer, the second node groove having a bottom surface lower than the interface;   a second node plug to penetrate the upper insulation layer in the second node groove to extend into the lower insulation layer, the second node plug being electrically connected to the lower substrate between the ground selection transistor and the lower cell transistors; and   a second connector to penetrate the upper insulation layer to electrically connect the upper substrate between the second node plug and the upper NAND string with the second node plug.