High-voltage metal-oxide-semiconductor device

Abstract

A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.

1 . A high-voltage MOS transistor, comprising:
 a gate overlying an active area of a semiconductor substrate;   a drain doping region of a first conductivity type pulled back away from an edge of the gate by a distance L;   a first lightly doped region of the first conductivity type between the gate and the drain doping region;   a source doping region of the first conductivity type in a first ion well of a second conductivity type; and   a second lightly doped region of the first conductivity type between the gate and the source doping region.   
     
     
         2 . The high voltage MOS transistor according to  claim 1 , wherein the semiconductor substrate is of the second conductivity type, the high voltage MOS transistor further comprises a second ion well of the first conductivity type in the semiconductor substrate for bulk isolation, wherein the first ion well is above the second ion well. 
     
     
         3 . The high voltage MOS transistor according to  claim 1  wherein a channel region is defined between the first and second lightly doped regions under the gate. 
     
     
         4 . The high voltage MOS transistor according to  claim 3  wherein the channel region comprises a first portion of the first ion well and a second portion of the semiconductor substrate. 
     
     
         5 . The high voltage MOS transistor according to  claim 3  further comprising a gate dielectric layer between the gate and the channel region. 
     
     
         6 . The high voltage MOS transistor according to  claim 1  wherein the gate comprises two portions: a first portion and a second portion, and wherein the first portion of the gate has a first concentration of dopants, the second portion, which is proximate to the drain doping region, has a second concentration of dopants. 
     
     
         7 . The high voltage MOS transistor according to  claim 6  wherein the second concentration is lower than the first concentration. 
     
     
         8 . The high voltage MOS transistor according to  claim 2  wherein the drain doping region is formed in the semiconductor substrate above the second ion well. 
     
     
         9 . The high voltage MOS transistor according to  claim 1  wherein the source doping region and the drain doping region are both formed in the first ion well. 
     
     
         10 . The high voltage MOS transistor according to  claim 1  wherein a shallow trench isolation (STI) region surrounds the active area. 
     
     
         11 . The high voltage MOS transistor according to  claim 1  wherein the gate comprises a sidewall spacer. 
     
     
         12 . A high-voltage MOS transistor, comprising:
 a gate overlying an active area of a semiconductor substrate;   a drain structure of a first conductivity type at one side of the gate, wherein the drain structure comprises a first heavily doping region spaced apart from a second heavily doping region that is proximate to the gate, a first lightly doped region interposed between the first and second heavily doping regions, and a second lightly doped region between the gate and the second heavily doping region;   a source doping region of the first conductivity type in a first ion well of a second conductivity type at the other side of the gate; and   a third lightly doped region of the first conductivity type between the gate and the source doping region.   
     
     
         13 . The high voltage MOS transistor according to  claim 12 , wherein the semiconductor substrate is of the second conductivity type, the high voltage MOS transistor further comprises a second ion well of the first conductivity type in the semiconductor substrate for bulk isolation, wherein the first ion well is above the second ion well. 
     
     
         14 . The high voltage MOS transistor according to  claim 12  wherein the drain structure is not formed in the first ion well. 
     
     
         15 . The high voltage MOS transistor according to  claim 12  wherein the drain structure, the source doping region and the third lightly doped region are formed in the first ion well. 
     
     
         16 . The high voltage MOS transistor according to  claim 12  wherein the gate comprises two portions: a first portion and a second portion, and wherein the first portion of the gate has a first concentration of dopants, the second portion, which is proximate to the drain doping region, has a second concentration of dopants. 
     
     
         17 . The high voltage MOS transistor according to  claim 16  wherein the second concentration is lower than the first concentration. 
     
     
         18 . The high voltage MOS transistor according to  claim 12  wherein a shallow trench isolation (STI) region surrounds the active area. 
     
     
         19 . The high voltage MOS transistor according to  claim 12  wherein the gate comprises a sidewall spacer.