Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates

Abstract

A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap.

1 . A semiconductor structure comprising:
 a germanium substrate comprising a first region and a second region;   a first silicon cap over the first region of the germanium substrate; and   a second silicon cap over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap.   
   
   
       2 . The semiconductor structure of  claim 1  further comprising:
 a PMOS device comprising a first gate dielectric over the first silicon cap; and   an NMOS device comprising a second gate dielectric over the second silicon cap.   
   
   
       3 . The semiconductor structure of  claim 2 , wherein the NMOS device further comprises a silicon germanium stressor in the germanium substrate and adjacent the second gate dielectric, and wherein the silicon germanium stressor has a germanium atomic percentage less than an atomic percentage of the germanium substrate. 
   
   
       4 . The semiconductor structure of  claim 2 , wherein the first gate dielectric and the second gate dielectric comprise high-k dielectric materials. 
   
   
       5 . The semiconductor structure of  claim 2 , wherein the first silicon cap contacts both the germanium substrate and the first gate dielectric, and the second silicon cap contacts both the germanium substrate and the second gate dielectric. 
   
   
       6 . The semiconductor structure of  claim 1 , wherein portions of the germanium substrate adjoining the first silicon cap and the second silicon cap are formed of substantially pure germanium. 
   
   
       7 . The semiconductor structure of  claim 1 , wherein the first thickness is less than the second thickness by a difference between than about 2 mono-layers of silicon (ML) and about 12 ML. 
   
   
       8 . The semiconductor structure of  claim 1 , wherein the first thickness is between about 2 ML and about 8 ML, and the second thickness is between about 4 ML and about 14 ML. 
   
   
       9 . The semiconductor structure of  claim 1 , wherein the second thickness is less than about 22 ML. 
   
   
       10 . The semiconductor structure of  claim 1 , wherein the first silicon cap and the second silicon cap are formed of substantially pure silicon. 
   
   
       11 . A semiconductor structure comprising:
 a germanium substrate comprising a top layer formed of substantially pure germanium, wherein the top layer comprises a first region and a second region;   a PMOS device comprising:
 a first silicon cap over the first region of the germanium substrate; and 
 a first gate dielectric over the first silicon cap; and 
   an NMOS device comprising:
 a second silicon cap over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap, and wherein the second thickness is less than about 22 mono-layers of silicon (ML); and 
 a second gate dielectric over the second silicon cap. 
   
   
   
       12 . The semiconductor structure of  claim 11 , wherein a first bottom of the first silicon cap is substantially level with a second bottom of the second silicon cap. 
   
   
       13 . The semiconductor structure of  claim 11 , wherein the first thickness is less than the second thickness by a difference between about 2 ML and about 12 ML. 
   
   
       14 . The semiconductor structure of  claim 11 , wherein the first thickness is between about 2 ML and about 8 ML. 
   
   
       15 . The semiconductor structure of  claim 11 , wherein the second thickness is between about 4 ML and about 14 ML. 
   
   
       16 . The semiconductor structure of  claim 11 , wherein the NMOS device further comprises a silicon germanium stressor adjacent the second gate dielectric and in the germanium substrate, wherein the silicon germanium stressor has a germanium atomic percentage less than an atomic percentage of the germanium substrate. 
   
   
       17 . The semiconductor structure of  claim 11 , wherein the first gate dielectric and the second gate dielectric comprise high-k dielectric materials. 
   
   
       18 . The semiconductor structure of  claim 11 , wherein the first silicon cap and the second silicon cap are formed of substantially pure silicon. 
   
   
       19 . The semiconductor structure of  claim 11 , wherein the first silicon cap adjoins the germanium substrate and the first gate dielectric, and the second silicon cap adjoins the germanium substrate and the second gate dielectric.