Semiconductor Devices and Methods of Manufacturing Thereof

Abstract

Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.

1 . A method of manufacturing a semiconductor device, the method comprising:
 forming a recess in a workpiece, the recess comprising a depth having a first dimension;   forming a first semiconductive material in the recess to partially fill the recess in a central region to a height comprising a second dimension, the second dimension comprising about one-half or greater of the first dimension, wherein the first semiconductive material lines a first sidewall of the recess proximate a channel region, and an opposite second sidewall proximate an isolation region;   forming a second semiconductive material over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.   
   
   
       2 . The method according to  claim 1 , wherein the first semiconductive material alters a stress of the workpiece in a region of the workpiece proximate the first semiconductive material. 
   
   
       3 . The method according to  claim 1 , wherein forming the first semiconductive material comprises filling the recess to a height comprising a second dimension wherein the second dimension comprises about three-quarters or greater of the first dimension. 
   
   
       4 . The method according to  claim 1 , wherein providing the workpiece comprises providing a workpiece comprised of the second semiconductive material. 
   
   
       5 . The method according to  claim 1 , further comprising forming a silicide over at least the second semiconductive material, and wherein forming the second semiconductive material comprises forming a material that improves the forming of the silicide. 
   
   
       6 . The method according to  claim 1 , wherein forming the first semiconductive material comprises forming SiGe, carbon-doped SiGe, or SiC, and wherein forming the second semiconductive material comprises forming Si. 
   
   
       7 . The method according to  claim 6 , wherein forming the first semiconductive material comprises epitaxially growing SiGe, carbon-doped SiGe, or SiC by introducing a first gas source of Si and introducing a second gas source of Ge and/or C, and wherein forming the second semiconductive material comprises epitaxially growing the second semiconductive material by continuing to introduce the first gas source while discontinuing the introduction of the second gas source. 
   
   
       8 . A method of manufacturing a transistor, the method comprising:
 forming a isolation region in a workpiece;   forming a gate dielectric material over the workpiece;   forming a gate material over the gate dielectric material;   patterning the gate material and the gate dielectric material to form a gate and a gate dielectric, the gate and the gate dielectric comprising sidewalls;   forming at least one sidewall spacer over the sidewalls of the gate and the gate dielectric;   recessing the workpiece proximate a first side and a second side of the gate and gate dielectric, the recess in the workpiece comprising a depth comprising a first dimension;   partially filling the recess in the workpiece in a central region with a first semiconductive material to a height comprising a second dimension, the second dimension comprising about one-half or greater of the first dimension, the first semiconductive material formed adjacent a first sidewall of the recess adjacent the gate, and an opposite second sidewall adjacent the isolation region; and   forming a second semiconductive material over the first semiconductive material to completely fill the recess in the workpiece, the second semiconductive material comprising a different material than the first semiconductive material.   
   
   
       9 . The method according to  claim 8 , wherein partially filling the recess in the workpiece in the central region with the first semiconductive material comprises: placing the workpiece in a processing chamber and epitaxially growing the first semiconductive material; and wherein forming the second semiconductive material comprises: after partially filling the recess with the first semiconductive material, without removing the workpiece from the processing chamber, epitaxially growing the second semiconductive material over the first semiconductive material. 
   
   
       10 . The method according to  claim 8 , wherein forming the second semiconductive material comprises overfilling the recess in the workpiece with the second semiconductive material above a top surface of the workpiece by about 0 to 50 nm. 
   
   
       11 . The method according to  claim 8 , wherein partially filling the recess in the workpiece in the central region with a first semiconductive material comprises depositing or epitaxially growing the first semiconductive material to completely fill the recess in the workpiece with the first semiconductive material, and then removing a top portion of the first semiconductive material from within the recess. 
   
   
       12 . The method according to  claim 11 , wherein removing the top portion of the first semiconductive material from within the recess comprises depositing a masking material over the workpiece, patterning the masking material to expose a portion of the first semiconductive material, and using the masking material as a mask while the exposed top portion of the first semiconductive material is etched away. 
   
   
       13 . The method according to  claim 12 , wherein patterning the masking material to expose the portion of the first semiconductive material comprises leaving a portion of the first semiconductive material adjacent to or proximate the gate and gate dielectric covered with the masking material. 
   
   
       14 . The method according to  claim 8 , wherein forming the second semiconductive material over the first semiconductive material comprises depositing or epitaxially growing the second semiconductive material. 
   
   
       15 . The method according to  claim 8 , wherein the method comprises forming first sidewall spacers over the sidewalls of the gate and the gate dielectric, before recessing the workpiece, further comprising forming second sidewall spacers over the first sidewall spacers, after forming the second semiconductive material. 
   
   
       16 . The method according to  claim 8 , wherein the method comprises forming first sidewall spacers over the sidewalls of the gate and the gate dielectric, and forming second sidewall spacers over the first sidewalls spacers, before recessing the workpiece. 
   
   
       17 . A method of manufacturing a transistor, the method comprising:
 forming a channel region within a workpiece;   forming a gate dielectric over the channel region;   forming a gate over the gate dielectric;   forming a first recess proximate a first side of the channel region;   forming a second recess proximate a second side of the channel region;   filling an upper portion adjacent to the channel region and a lower portion of the first and the second recesses with a first semiconductive material, wherein the first semiconductive material comprises a first thickness in a central region;   depositing a second semiconductive material over the first semiconductive material thereby filling the first and second recesses, the second semiconductive material being different than the first semiconductive material, the second semiconductive material comprising a second thickness, wherein the first thickness is equal to or greater than the second thickness; and   forming a silicide over the first and the second semiconductive material, wherein the silicide contacts the first and the second semiconductive material.   
   
   
       18 . The method according to  claim 17 , wherein the first and the second recesses comprise a first width, wherein the second semiconductive material comprises a top surface having a second width, the second width being about 80% or greater of the first width. 
   
   
       19 . The method according to  claim 17 , further comprising forming a silicide disposed over and adjacent to the gate. 
   
   
       20 . The method according to  claim 17 , wherein the transistor comprises a p channel metal oxide semiconductor (PMOS) field effect transistor (FET), and wherein the first semiconductive material increases a compressive stress of the channel region. 
   
   
       21 . The method according to  claim 17 , wherein the transistor comprises an n channel metal oxide semiconductor (NMOS) field effect transistor (FET), and wherein the first semiconductive material increases a tensile stress of the channel region.