Interface circuit

Abstract

A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.

1 - 9 . (canceled) 
     
     
         10 . A data processing system comprising:
 a memory; and   a memory controller for transferring data with said memory, wherein   said memory controller including:   a data receiving circuit for receiving data read from memory to produce internal read data;   a preamble detecting circuit for detecting a preamble of data transfer according to a data strobe signal applied from said memory;   a data transfer control circuit for controlling a read operation of said data receiving circuit according to a detection signal applied from said preamble detecting circuit to perform control operations necessary for the data transfer with said memory; and   a command issuing unit for issuing a command to said memory under the control of said data transfer control circuit, wherein   said preamble detecting circuit having:   a delay line for delaying said data strobe signal; and   a detector circuit for detecting an expiration of a preamble period that indicates a start of the transfer of data according to said data strobe signal and an output signal of said delay line.   
     
     
         11 . The data processing system according to  claim 10  further comprising;
 a processing circuit,   wherein said processing circuit applies a data request to said memory controller and receives said internal read data.