Cmos semiconductor device and method for manufacturing the same

Abstract

A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material.

1 . A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising:
 a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and   a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein   the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material.   
     
     
         2 . The CMOS semiconductor device according to  claim 1 , wherein
 the first insulation layer is composed of the high-k material containing an element which is not contained in the second insulation layer, and the second insulation layer is composed of the high-k material containing an element which is not contained in the first insulation layer.   
     
     
         3 . The CMOS semiconductor device according to  claim 1  or  2 , wherein
 the first insulation layer and the second insulation layer are each composed of the high-k material containing three or more kinds of elements in which only one kind is different from all the others and the others are the same.   
     
     
         4 . The CMOS semiconductor device according to any one of  claims 1  to  3 , wherein
 the first insulation layer is composed of HfLaO or HfMgO, and the second insulation layer is composed of HfAlO.   
     
     
         5 . A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising:
 a gate electrode of the n-type MOSFET having a first insulation layer containing a high-k material and a cap material, and a first metal layer provided on the first insulation layer and composed of a metal material; and   a gate electrode of the p-type MOSFET having a second insulation layer containing a high-k material and a cap material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein   the first insulation layer and the second insulation layer are each composed of the same high-k material and the cap materials different from one another, and the first metal layer and the second metal layer are composed of the same metal material.   
     
     
         6 . The CMOS semiconductor device according to  claim 5 , wherein
 the first insulation layer is composed of a common high-k material layer formed on a surface of a semiconductor substrate, and a first cap material layer formed thereon, the second insulation layer is composed of a common high-k material layer formed on the surface of the semiconductor substrate, and a second cap material layer formed thereon, and the first cap material layer or the second cap material layer covers the semiconductor substrate positioned between the gate electrode of the n-type MOSFET and the gate electrode of the p-type MOSFET.   
     
     
         7 . The CMOS semiconductor device according to  claim 5  or  6 , wherein
 the first insulation layer comprises the high-k material layer composed of HfO 2 , HfSiO or its nitride, and the cap material layer composed of LaO or MgO, and   the second insulation layer comprises the high-k material layer composed of HfO 2 , HfSiO or its nitride, and the cap material layer composed of AlO.   
     
     
         8 . The CMOS semiconductor device according to any one of  claims 1  to  7 , wherein
 the first metal layer and the second metal layer are each composed of one material selected from a group including TiN, TaN, TaSiN, NiSi, PtSi, and CoSi 2 .   
     
     
         9 . A method for producing a CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising the steps of:
 preparing a semiconductor substrate defined by an n-type MOSFET formation region and a p-type MOSFET formation region;   forming a high-k material layer, a first cap layer, and a first metal layer sequentially on the semiconductor substrate;   removing the first cap layer and the first metal layer except for those in the p-type MOSFET formation region;   forming a second cap layer and a second metal layer sequentially on the semiconductor substrate;   removing the second metal layer except for that in the n-type MOSFET formation region;   removing the second cap layer provided between the n-type MOSFET formation region and the p-type MOSFET formation region, using the first metal layer and the second metal layer as masks;   removing the first metal layer and the second metal layer;   forming a gate metal material layer on the semiconductor substrate; and   forming a gate metal layer of a gate electrode of each of the n-type MOSFET and the p-type MOSFET by etching the gate metal material layer in the same etching step.   
     
     
         10 . A method for producing a CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising the steps of:
 preparing a semiconductor substrate defined by an n-type MOSFET formation region and a p-type MOSFET formation region;   forming a high-k material layer, a first cap layer, a first metal layer, and a first silicon insulation layer sequentially on the semiconductor substrate;   removing the first cap layer, the first metal layer, and the first silicon insulation layer except for those in the p-type MOSFET formation region;   forming a second cap layer, a second metal layer, and a second silicon insulation layer sequentially on the semiconductor substrate;   removing the second metal layer and the second silicon insulation layer except for those in the n-type MOSFET formation region;   removing the second cap layer provided between the n-type MOSFET formation region and the p-type MOSFET formation region, using the first silicon insulation layer and the second silicon insulation layer as masks;   removing the first silicon insulation layer and the second silicon insulation layer;   removing the first metal layer and the second metal layer;   forming a gate metal material layer on the semiconductor substrate; and   forming a gate metal layer of a gate electrode of each of the n-type MOSFET and the p-type MOSFET by etching the gate metal material layer in the same etching step.   
     
     
         11 . The method for producing a CMOS semiconductor device according to  claim 9  or  10 , wherein
 the gate metal material layer has a laminated structure of a mid-gap material layer and a low-resistance material layer.   
     
     
         12 . The method for producing a CMOS semiconductor device according to  claim 11 , wherein
 the mid-gap material is composed of TiN, and the low-resistance material is composed of W.   
     
     
         13 . A method for producing a CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising steps of:
 preparing a semiconductor substrate defined by an n-type MOSFET formation region and a p-type MOSFET formation region;   forming a high-k material layer, a first cap layer, a first metal layer, and a first silicon insulation layer sequentially on the semiconductor substrate;   removing the first cap layer, the first metal layer, and the first silicon insulation layer except for those in the p-type MOSFET formation region;   forming a second cap layer, a second metal layer, and a second silicon insulation layer sequentially on the semiconductor substrate;   removing the second metal layer and the second silicon insulation layer except for those in the n-type MOSFET formation region;   removing the second cap layer formed on a side wall or an upper surface of the first metal layer and the first silicon insulation layer;   removing the first silicon insulation layer and the second silicon insulation layer.   removing the first metal layer and the second metal layer;   forming a gate metal material layer on the semiconductor substrate; and   forming a gate metal layer of a gate electrode of each of the n-type MOSFET and the p-type MOSFET by etching the gate metal material layer in the same etching step.   
     
     
         14 . The method for producing a CMOS semiconductor device according to any one of  claims 9  to  13 , wherein
 the first metal layer and the second metal layer are each composed of one material selected from a group including TiN, TaN, TaSiN, NiSi, PtSi, and CoSi 2 .   
     
     
         15 . The method for producing a CMOS semiconductor device according to any one of  claims 10  to  13 , wherein
 the first silicon insulation layer and the second silicon insulation layer are each composed of silicon nitride.   
     
     
         16 . A method for producing a CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising the steps of:
 preparing a semiconductor substrate defined by an n-type MOSFET formation region and a p-type MOSFET formation region;   forming a high-k material layer and an amorphous silicon layer, on the semiconductor substrate;   implanting first metal ions in the amorphous silicon in the p-type MOSFET formation region;   implanting second metal ions in the amorphous silicon in the n-type MOSFET formation region;   segregating a first segregated layer of a first metal and a second segregated layer of a second metal, in a boundary between the high-k material layer and the amorphous silicon layer by a heat treatment;   removing the amorphous silicon layer;   making a first cap layer and a second cap layer by oxidizing the first segregated layer and the second segregated layer;   forming a gate metal material layer on the semiconductor substrate; and   forming a gate metal layer of a gate electrode of each of the n-type MOSFET and the p-type MOSFET, by etching the gate metal material layer in the same etching step.   
     
     
         17 . A method for producing a CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising the steps of:
 preparing a semiconductor substrate defined by an n-type MOSFET formation region and a p-type MOSFET formation region;   forming a high-k material layer and a silicon layer, on the semiconductor substrate;   depositing a first metal on the silicon layer in the p-type MOSFET formation region;   segregating a first segregated layer of the first Metal, in a boundary between the high-k material layer and the silicon layer by a heat treatment;   forming a deposit layer of a second metal, on the silicon layer in the n-type MOSFET formation region;   segregating a second segregated layer of the second metal, in a boundary between the high-k material layer and the silicon layer by a heat treatment;   removing the silicon layer;   making a first cap layer and a second cap layer by oxidizing the first segregated layer and the second segregated layer;   forming a gate metal material layer on the semiconductor substrate; and   forming a gate metal layer of a gate electrode of each of the n-type MOSFET and the p-type MOSFET, by etching the gate metal material layer in the same etching step.   
     
     
         18 . A method for producing a CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising the steps of:
 preparing a semiconductor substrate defined by an n-type MOSFET formation region and a p-type MOSFET formation region;   forming a high-k material layer on the semiconductor substrate;   forming a first cap metal layer in the n-type MOSFET formation region and a second cap metal layer in the p-type MOSFET formation region;   forming a polycrystalline silicon layer on the semiconductor substrate;   forming a polycrystalline silicon gate layer in each of the n-type MOSFET formation region and the p-type MOSFET formation region, by etching the polycrystalline silicon layer in the same etching step; and   making the polycrystalline silicon gate layers of the n-type MOSFET formation region and the p-type MOSFET formation region into silicide metal gate layers composed of different materials.   
     
     
         19 . A method for producing a CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising the steps of:
 preparing a semiconductor substrate defined by an n-type MOSFET formation region and a p-type MOSFET formation region;   forming a high-k material layer and a polycrystalline silicon layer, on the semiconductor substrate;   forming a polycrystalline silicon gate layer in each of the n-type MOSFET formation region and the p-type MOSFET formation region, by etching at least the polycrystalline silicon layer in the same etching step; and   forming an insulation layer to cover the polycrystalline silicon gate layer, on the semiconductor substrate, and forming an interlayer insulation layer provided by reducing a film thickness of the insulation layer to expose an upper part of the polycrystalline silicon gate layer;   removing the polycrystalline silicon gate in the n-type MOSFET formation region and forming a first cap layer and a gate metal layer instead; and   removing the polycrystalline silicon gate in the p-type MOSFET formation region and forming a second cap layer and a gate metal layer instead.