Nonvolatile Memory Devices and Related Methods

Abstract

Nonvolatile memory devices and methods of fabricating the same are provided. A semiconductor substrate is provided having a cell field region and a high-voltage field region. Device isolation films are provided on the substrate. The device isolation films define active regions of the substrate. A cell gate-insulation film and a cell gate-conductive film are provided on the cell field region of the substrate including the device isolation films. A high-voltage gate-insulation film and a high-voltage gate-conductive film are provided on the high-voltage field region of the substrate including the device isolation films. The device isolation film on the high-voltage field region of the substrate is at least partially recessed to provide a groove therein.

1 . A nonvolatile memory device comprising:
 a semiconductor substrate having a cell field region and a high-voltage field region;   device isolation films on the substrate, the device isolation films defining active regions of the substrate;   a cell gate-insulation film and a cell gate-conductive film on the cell field region of the substrate including the device isolation films; and   a high-voltage gate-insulation film and a high-voltage gate-conductive film on the high-voltage field region of the substrate including the device isolation films, wherein the device isolation film on the high-voltage field region of the substrate is at least partially recessed to provide a groove therein.   
     
     
         2 . The nonvolatile memory device of  claim 1 , wherein a depth of the groove is larger than a thickness of the high-voltage gate-insulation film. 
     
     
         3 . The nonvolatile memory device of  claim 2 , wherein an upper surface of the device isolation film in the cell field region is recessed. 
     
     
         4 . The nonvolatile memory device of  claim 2 , wherein the cell gate-insulation film comprises a tunneling insulation film on the substrate, a charge storage film on the tunneling insulating film and a blocking insulation film on the charge storage film. 
     
     
         5 . The nonvolatile memory device of  claim 2 , further comprising a common gate-conductive film on the high-voltage gate-conductive film and the cell gate-conductive film, wherein the high-voltage gate-conductive film includes an opening on the groove and the common gate-conductive film is provided in the groove and opening. 
     
     
         6 . The nonvolatile memory device of  claim 1 , wherein a thickness of the high-voltage gate-insulation film is smaller than a distance between an edge of the device isolation film and the groove. 
     
     
         7 . The nonvolatile memory device of  claim 6 , wherein an upper surface of the device isolation film in the cell field region is recessed. 
     
     
         8 . The nonvolatile memory device of  claim 6 , wherein the cell gate-insulation film comprises a tunneling insulation film on the substrate, a charge storage film on the tunneling insulating film and a blocking insulation film on the charge storage film. 
     
     
         9 . The nonvolatile memory device of  claim 6 , further comprising a common gate-conductive film on the high-voltage gate-conductive film and the cell gate-conductive film, wherein the high-voltage gate-conductive film includes an opening on the groove and the common gate-conductive film is provided in the groove and opening. 
     
     
         10 . The nonvolatile memory device of  claim 9 , wherein the cell gate-insulation film is formed between a sidewall of the groove and the opening, and the common gate-conductive film. 
     
     
         11 . A method of fabricating a nonvolatile memory device, the method comprising:
 forming device isolation films on a semiconductor substrate having a cell field region, a high-voltage field region, and a low-voltage field region, the device isolation films defining active regions of the substrate;   forming a high-voltage gate-insulation film on the high-voltage field region of the substrate;   forming a low-voltage gate-insulation film on the cell field region and the low-voltage field region of the substrate;   forming a mask on the substrate that reveals at least a portion of the cell field region and the device isolation film of the high-voltage field region;   implanting impurities into the substrate according to the mask;   removing the low-voltage gate-insulation film and the high-voltage gate-insulation film from the substrate according to the mask;   forming a cell gate-insulation film on the cell field region of the substrate; and   forming a common gate-conductive film on the substrate.   
     
     
         12 . The method of  claim 11 , wherein removing is followed by etching the device isolation film of the high-voltage field region and the device isolation film of the cell field region according to the mask. 
     
     
         13 . The method of  claim 11 , wherein implanting the impurities comprises implanting ions for controlling threshold voltages in the cell field region and channel stop in the high-voltage field region.