Package structure for integrated circuit device and method of the same

Abstract

A package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of intergraded circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of intergraded circuit devices and on a sidewall of it.

1 . A method of forming a package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer, the method comprising:
 forming at least one groove in the wafer;   forming an extension metal pad electrically contacting the at least one of the plurality of intergraded circuit devices;   forming a first conductive bump on the extension metal pad;   forming an insulator layer over the plurality of intergraded circuit devices and in the at least one groove; and   cutting the wafer at the at least one groove to obtain a plurality of packaged chips;   wherein the insulator layer covers a sidewall of the at least one of the plurality of intergraded circuit devices.   
     
     
         2 . The method of  claim 1 , further comprising:
 assembling at least one of the plurality of packaged chips to a substrate having an interconnect structure.   
     
     
         3 . The method of  claim 1 , further comprising:
 forming a second conductive bump on the first conductive bump; and   forming a surface metal layer on the second conductive bump.   
     
     
         4 . The method of  claim 1 , further comprising:
 forming a metal wall on the first conductive bump.   
     
     
         5 . The method of  claim 1 , further comprising:
 forming a metal pad between the at least one of the plurality of integrated circuit devices and the extension metal pad, so that the extension metal pad electrically contacts the at least one of the plurality of the integrated circuit devices;   wherein an area of the extension metal pad is bigger than an area of the metal pad.   
     
     
         6 . The method of  claim 5 , further comprising:
 forming a passivation layer between the at least one of the plurality of integrated circuit devices and the extension metal pad.   
     
     
         7 . The method of  claim 3 , wherein at least one of the step of forming the first conductive bump on the extension metal pad and the step of forming the second conductive bump on the first conductive bump comprises forming a conductive bump having a plurality of metal particles and a polymer compound. 
     
     
         8 . The method of  claim 1 , wherein the step of forming the insulator layer over the plurality of intergraded circuit devices and in the at least one groove comprises printing an insulator layer over the plurality of intergraded circuit devices and in the at least one groove. 
     
     
         9 . The method of  claim 8 , wherein a volume ratio of the plurality metal particles to the polymer compound is greater than 85:15. 
     
     
         10 . The method of  claim 1 , wherein the step of forming the insulator layer over the plurality of intergraded circuit devices and in the at least one groove comprises:
 covering the first conductive bump by the insulator layer; and   removing a portion of the insulator layer to expose the first conductive bump.